Add another FP recoding test case

[riscv-tests.git] / isa / rv64uv / vvadd_w.S

diff --git a/isa/rv64uv/vvadd_w.S b/isa/rv64uv/vvadd_w.S
index 6e194b22fe6ebc8c3616814127e4c8661c3b462d..842f2652fdf024ec23b2e4b9998d50d1fe0cf010 100644 (file)
--- a/isa/rv64uv/vvadd_w.S
+++ b/isa/rv64uv/vvadd_w.S
@@ -1,3 +1,5 @@
+# See LICENSE for license details.
+
 #*****************************************************************************
 # vvadd_w.S
 #-----------------------------------------------------------------------------
@@ -8,7 +10,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 32,0
@@ -26,16 +28,16 @@ RVTEST_CODE_BEGIN
   fence
   lw a1,0(a5)
   li a2,10
-  li x28,2
+  li TESTNUM,2
   bne a1,a2,fail
   lw a1,4(a5)
-  li x28,3
+  li TESTNUM,3
   bne a1,a2,fail
   lw a1,8(a5)
-  li x28,4
+  li TESTNUM,4
   bne a1,a2,fail
   lw a1,12(a5)
-  li x28,5
+  li TESTNUM,5
   bne a1,a2,fail
   j pass