from litex.soc.cores.led import LedChaser
from litedram.modules import IS42S16160
-from litedram.phy import GENSDRPHY
+from litedram.phy import GENSDRPHY, HalfRateGENSDRPHY
# CRG ----------------------------------------------------------------------------------------------
class _CRG(Module):
- def __init__(self, platform, sys_clk_freq):
+ def __init__(self, platform, sys_clk_freq, sdram_rate="1:1"):
self.clock_domains.cd_sys = ClockDomain()
- self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True)
+ if sdram_rate == "1:2":
+ self.clock_domains.cd_sys2x = ClockDomain()
+ self.clock_domains.cd_sys2x_ps = ClockDomain(reset_less=True)
+ else:
+ self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True)
# # #
self.submodules.pll = pll = CycloneIVPLL(speedgrade="-6")
pll.register_clkin(clk50, 50e6)
pll.create_clkout(self.cd_sys, sys_clk_freq)
- pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90)
+ if sdram_rate == "1:2":
+ pll.create_clkout(self.cd_sys2x, 2*sys_clk_freq)
+ pll.create_clkout(self.cd_sys2x_ps, 2*sys_clk_freq, phase=90)
+ else:
+ pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90)
# SDRAM clock
- self.specials += DDROutput(1, 0, platform.request("sdram_clock"), ClockSignal("sys_ps"))
+ sdram_clk = ClockSignal("sys2x_ps" if sdram_rate == "1:2" else "sys_ps")
+ self.specials += DDROutput(1, 0, platform.request("sdram_clock"), sdram_clk)
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
- def __init__(self, sys_clk_freq=int(50e6), **kwargs):
+ def __init__(self, sys_clk_freq=int(50e6), sdram_rate="1:1", **kwargs):
platform = de0nano.Platform()
# SoCCore ----------------------------------------------------------------------------------
**kwargs)
# CRG --------------------------------------------------------------------------------------
- self.submodules.crg = _CRG(platform, sys_clk_freq)
+ self.submodules.crg = _CRG(platform, sys_clk_freq, sdram_rate=sdram_rate)
# SDR SDRAM --------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
- self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
+ sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY
+ self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"))
self.add_sdram("sdram",
phy = self.sdrphy,
- module = IS42S16160(sys_clk_freq, "1:1"),
+ module = IS42S16160(sys_clk_freq, sdram_rate),
origin = self.mem_map["main_ram"],
size = kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size = kwargs.get("l2_size", 8192),
parser = argparse.ArgumentParser(description="LiteX SoC on DE0-Nano")
parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load", action="store_true", help="Load bitstream")
+ parser.add_argument("--sdram-rate", default="1:1", help="SDRAM Rate 1:1 Full Rate (default), 1:2 Half Rate")
builder_args(parser)
soc_sdram_args(parser)
args = parser.parse_args()
- soc = BaseSoC(**soc_sdram_argdict(args))
+ soc = BaseSoC(sdram_rate=args.sdram_rate, **soc_sdram_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder.build(run=args.build)