build/sim: improve timebase calculation (strict checks) and update modules

[litex.git] / litex / build / sim / core / modules.h

diff --git a/litex/build/sim/core/modules.h b/litex/build/sim/core/modules.h
index b6aa4b46fcee3cd1b8912090ab1556f476194ae6..96104211345fcace017da2e9ec40d4a47181f9e6 100644 (file)
--- a/litex/build/sim/core/modules.h
+++ b/litex/build/sim/core/modules.h
@@ -4,6 +4,7 @@
 #define __MODULE_H_
 
 #include <stdint.h>
+#include <stdbool.h>
 #include "pads.h"
 
 struct interface_s {
@@ -34,8 +35,24 @@ struct ext_module_list_s {
   struct ext_module_list_s *next;
 };
 
+struct clk_edge_t {
+  int last_clk;
+};
+
 int litex_sim_file_parse(char *filename, struct module_s **mod, uint64_t *timebase);
 int litex_sim_load_ext_modules(struct ext_module_list_s **mlist);
 int litex_sim_find_ext_module(struct ext_module_list_s *first, char *name , struct ext_module_list_s **found);
 
+inline bool clk_pos_edge(struct clk_edge_t *edge, int new_clk) {
+  bool is_edge = edge->last_clk == 0 && new_clk == 1;
+  edge->last_clk = new_clk;
+  return is_edge;
+}
+
+inline bool clk_neg_edge(struct clk_edge_t *edge, int new_clk) {
+  bool is_edge = edge->last_clk == 1 && new_clk == 0;
+  edge->last_clk = new_clk;
+  return is_edge;
+}
+
 #endif