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cpu/zynq7000: set csr map to 0x00000000.
[litex.git]
/
litex
/
soc
/
cores
/
cpu
/
zynq7000
/
core.py
diff --git
a/litex/soc/cores/cpu/zynq7000/core.py
b/litex/soc/cores/cpu/zynq7000/core.py
index 9ed783a8adc0a2f9f85a31b575ed1a4f3d1ab95a..91d7692e9068f61af801a30a04d0f6bd929e8fa6 100644
(file)
--- a/
litex/soc/cores/cpu/zynq7000/core.py
+++ b/
litex/soc/cores/cpu/zynq7000/core.py
@@
-24,6
+24,10
@@
class Zynq7000(CPU):
nop = "nop"
io_regions = {0x00000000: 0x100000000} # origin, length
+ @property
+ def mem_map(self):
+ return {"csr": 0x00000000}
+
def __init__(self, platform, variant):
self.platform = platform
self.reset = Signal()