soc/cores/cpu/vexriscv_smp integration

[litex.git] / litex_setup.py

diff --git a/litex_setup.py b/litex_setup.py
index fde423c17b343708f850404d266da6c67279e6d6..9eb91a7f976fa59d551c6f27ec1a45f65053f567 100755 (executable)
--- a/litex_setup.py
+++ b/litex_setup.py
@@ -46,6 +46,7 @@ repos = [
     ("pythondata-cpu-picorv32",    ("https://github.com/litex-hub/", False, True, None)),
     ("pythondata-cpu-serv",        ("https://github.com/litex-hub/", False, True, None)),
     ("pythondata-cpu-vexriscv",    ("https://github.com/litex-hub/", False, True, None)),
+    ("pythondata-cpu-vexriscv_smp",("https://github.com/litex-hub/", True,  True, None)),
     ("pythondata-cpu-rocket",      ("https://github.com/litex-hub/", False, True, None)),
     ("pythondata-cpu-minerva",     ("https://github.com/litex-hub/", False, True, None)),
     ("pythondata-cpu-microwatt",   ("https://github.com/litex-hub/", False, True, 0xba76652)),