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add ghdl wishbone basic test
[soc-cocotb-sim.git] / ls180 / post_pnr / cocotb / Makefile
diff --git a/ls180/post_pnr/cocotb/Makefile b/ls180/post_pnr/cocotb/Makefile
index 1255036a575644b2c41a4e7169cbba125392bf2d..006c168beb8555df515f24a90fb29848f48e8c2a 100644 (file)
--- a/ls180/post_pnr/cocotb/Makefile
+++ b/ls180/post_pnr/cocotb/Makefile
@@ -15,7 +15,7 @@ VHDL_SOURCES = \
   $(wildcard $(VSTDIR)/*.vst) \
   $(wildcard $(NSXLIBDIR)/*.vhd) \
   $(wildcard $(NIOLIBDIR)/*.vhd)
-TOPLEVEL=corona
+TOPLEVEL=ls180
 TOPLEVEL_LANG=vhdl
 MODULE=test
 SIM=ghdl