Add Tercel PHY reset synchronization

[microwatt.git] / microwatt.core

diff --git a/microwatt.core b/microwatt.core
index 4f9820ab2d0969aa481068d57c46bcb650607704..79af3c12bc72cb762cb25461e1e9e04737db760a 100644 (file)
--- a/microwatt.core
+++ b/microwatt.core
@@ -19,10 +19,9 @@ filesets:
       - sim_console.vhdl
       - logical.vhdl
       - countzero.vhdl
-      - gpr_hazard.vhdl
-      - cr_hazard.vhdl
       - control.vhdl
       - execute1.vhdl
+      - fpu.vhdl
       - loadstore1.vhdl
       - mmu.vhdl
       - dcache.vhdl
@@ -64,6 +63,8 @@ filesets:
   xilinx_specific:
     files:
       - xilinx-mult.vhdl : {file_type : vhdlSource-2008}
+      - fpga/fpga-random.vhdl : {file_type : vhdlSource-2008}
+      - fpga/fpga-random.xdc : {file_type : xdc}
 
   debug_xilinx:
     files:
@@ -85,6 +86,18 @@ filesets:
       - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
       - fpga/top-nexys-video.vhdl : {file_type : vhdlSource-2008}
 
+  acorn_cle_215:
+    files:
+      - fpga/acorn-cle-215.xdc : {file_type : xdc}
+      - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
+      - fpga/top-acorn-cle-215.vhdl : {file_type : vhdlSource-2008}
+
+  genesys2:
+    files:
+      - fpga/genesys2.xdc : {file_type : xdc}
+      - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
+      - fpga/top-genesys2.vhdl : {file_type : vhdlSource-2008}
+
   arty_a7:
     files:
       - fpga/arty_a7.xdc : {file_type : xdc}
@@ -103,10 +116,13 @@ filesets:
   liteeth:
       depend : [":microwatt:liteeth"]
 
+  uart16550:
+      depend : ["::uart16550"]
+
 targets:
   nexys_a7:
     default_tool: vivado
-    filesets: [core, nexys_a7, soc, fpga, debug_xilinx, xilinx_specific]
+    filesets: [core, nexys_a7, soc, fpga, debug_xilinx, uart16550, xilinx_specific]
     parameters :
       - memory_size
       - ram_init_file
@@ -114,13 +130,83 @@ targets:
       - clk_frequency
       - disable_flatten_core
       - log_length=2048
+      - uart_is_16550
+      - has_fpu
+      - has_btc
     tools:
       vivado: {part : xc7a100tcsg324-1}
     toplevel : toplevel
 
+  acorn-cle-215-nodram:
+    default_tool: vivado
+    filesets: [core, acorn_cle_215, soc, fpga, debug_xilinx, uart16550, xilinx_specific]
+    parameters :
+      - memory_size
+      - ram_init_file
+      - clk_input
+      - clk_frequency
+      - disable_flatten_core
+      - spi_flash_offset=10485760
+      - log_length=2048
+      - uart_is_16550
+    tools:
+      vivado: {part : xc7a200tsbg484-2}
+    toplevel : toplevel
+
+  genesys2-nodram:
+    default_tool: vivado
+    filesets: [core, genesys2, soc, fpga, debug_xilinx, uart16550, xilinx_specific]
+    parameters :
+      - memory_size
+      - ram_init_file
+      - clk_frequency
+      - use_litedram=false
+      - no_bram=false
+      - disable_flatten_core
+      - spi_flash_offset=10485760
+      - log_length=2048
+      - uart_is_16550=false
+    tools:
+      vivado: {part : xc7k325tffg900-2}
+    toplevel : toplevel
+
+  acorn-cle-215:
+    default_tool: vivado
+    filesets: [core, acorn_cle_215, soc, fpga, debug_xilinx, litedram, uart16550, xilinx_specific]
+    parameters :
+      - memory_size
+      - ram_init_file
+      - use_litedram=true
+      - disable_flatten_core
+      - no_bram
+      - spi_flash_offset=10485760
+      - log_length=2048
+      - uart_is_16550
+    generate: [litedram_acorn_cle_215]
+    tools:
+      vivado: {part : xc7a200tsbg484-2}
+    toplevel : toplevel
+
+  genesys2:
+    default_tool: vivado
+    filesets: [core, genesys2, soc, fpga, debug_xilinx, litedram, uart16550, xilinx_specific]
+    parameters :
+      - memory_size
+      - ram_init_file
+      - use_litedram=true
+      - disable_flatten_core
+      - no_bram
+      - spi_flash_offset=10485760
+      - log_length=2048
+      - uart_is_16550=false
+    generate: [litedram_genesys2]
+    tools:
+      vivado: {part : xc7k325tffg900-2}
+    toplevel : toplevel
+
   nexys_video-nodram:
     default_tool: vivado
-    filesets: [core, nexys_video, soc, fpga, debug_xilinx, xilinx_specific]
+    filesets: [core, nexys_video, soc, fpga, debug_xilinx, uart16550, xilinx_specific]
     parameters :
       - memory_size
       - ram_init_file
@@ -129,13 +215,16 @@ targets:
       - disable_flatten_core
       - spi_flash_offset=10485760
       - log_length=2048
+      - uart_is_16550
+      - has_fpu
+      - has_btc
     tools:
       vivado: {part : xc7a200tsbg484-1}
     toplevel : toplevel
 
   nexys_video:
     default_tool: vivado
-    filesets: [core, nexys_video, soc, fpga, debug_xilinx, litedram, xilinx_specific]
+    filesets: [core, nexys_video, soc, fpga, debug_xilinx, litedram, uart16550, xilinx_specific]
     parameters:
       - memory_size
       - ram_init_file
@@ -144,6 +233,9 @@ targets:
       - no_bram
       - spi_flash_offset=10485760
       - log_length=2048
+      - uart_is_16550
+      - has_fpu
+      - has_btc
     generate: [litedram_nexys_video]
     tools:
       vivado: {part : xc7a200tsbg484-1}
@@ -151,7 +243,7 @@ targets:
 
   arty_a7-35-nodram:
     default_tool: vivado
-    filesets: [core, arty_a7, soc, fpga, debug_xilinx, xilinx_specific]
+    filesets: [core, arty_a7, soc, fpga, debug_xilinx, uart16550, xilinx_specific]
     parameters :
       - memory_size
       - ram_init_file
@@ -160,13 +252,17 @@ targets:
       - disable_flatten_core
       - spi_flash_offset=3145728
       - log_length=512
+      - uart_is_16550
+      - has_uart1
+      - has_fpu=false
+      - has_btc=false
     tools:
       vivado: {part : xc7a35ticsg324-1L}
     toplevel : toplevel
 
   arty_a7-35:
     default_tool: vivado
-    filesets: [core, arty_a7, soc, fpga, debug_xilinx, litedram, liteeth, xilinx_specific]
+    filesets: [core, arty_a7, soc, fpga, debug_xilinx, litedram, liteeth, uart16550, xilinx_specific]
     parameters :
       - memory_size
       - ram_init_file
@@ -176,6 +272,10 @@ targets:
       - no_bram
       - spi_flash_offset=3145728
       - log_length=512
+      - uart_is_16550
+      - has_uart1
+      - has_fpu=false
+      - has_btc=false
     generate: [litedram_arty, liteeth_arty]
     tools:
       vivado: {part : xc7a35ticsg324-1L}
@@ -183,7 +283,7 @@ targets:
 
   arty_a7-100-nodram:
     default_tool: vivado
-    filesets: [core, arty_a7, soc, fpga, debug_xilinx, xilinx_specific]
+    filesets: [core, arty_a7, soc, fpga, debug_xilinx, uart16550, xilinx_specific]
     parameters :
       - memory_size
       - ram_init_file
@@ -192,13 +292,17 @@ targets:
       - disable_flatten_core
       - spi_flash_offset=4194304
       - log_length=2048
+      - uart_is_16550
+      - has_uart1
+      - has_fpu
+      - has_btc
     tools:
       vivado: {part : xc7a100ticsg324-1L}
     toplevel : toplevel
 
   arty_a7-100:
     default_tool: vivado
-    filesets: [core, arty_a7, soc, fpga, debug_xilinx, litedram, liteeth, xilinx_specific]
+    filesets: [core, arty_a7, soc, fpga, debug_xilinx, litedram, liteeth, uart16550, xilinx_specific]
     parameters:
       - memory_size
       - ram_init_file
@@ -208,6 +312,10 @@ targets:
       - no_bram
       - spi_flash_offset=4194304
       - log_length=2048
+      - uart_is_16550
+      - has_uart1
+      - has_fpu
+      - has_btc
     generate: [litedram_arty, liteeth_arty]
     tools:
       vivado: {part : xc7a100ticsg324-1L}
@@ -215,7 +323,7 @@ targets:
 
   cmod_a7-35:
     default_tool: vivado
-    filesets: [core, cmod_a7-35, soc, fpga, debug_xilinx, xilinx_specific]
+    filesets: [core, cmod_a7-35, soc, fpga, debug_xilinx, uart16550, xilinx_specific]
     parameters :
       - memory_size
       - ram_init_file
@@ -224,6 +332,9 @@ targets:
       - clk_frequency
       - disable_flatten_core
       - log_length=512
+      - uart_is_16550
+      - has_fpu=false
+      - has_btc=false
     tools:
       vivado: {part : xc7a35tcpg236-1}
     toplevel : toplevel
@@ -247,6 +358,14 @@ generate:
     generator: litedram_gen
     parameters: {board : nexys-video}
 
+  litedram_acorn_cle_215:
+    generator: litedram_gen
+    parameters: {board : acorn-cle-215}
+
+  litedram_genesys2:
+    generator: litedram_gen
+    parameters: {board : genesys2}
+
 parameters:
   memory_size:
     datatype    : int
@@ -276,6 +395,18 @@ parameters:
     paramtype   : generic
     default     : 100000000
 
+  has_fpu:
+    datatype    : bool
+    description : Include a floating-point unit in the core
+    paramtype   : generic
+    default     : true
+
+  has_btc:
+    datatype    : bool
+    description : Include a branch target cache in the core
+    paramtype   : generic
+    default     : true
+
   disable_flatten_core:
     datatype    : bool
     description : Prevent Vivado from flattening the main core components
@@ -294,6 +425,18 @@ parameters:
     paramtype   : generic
     default     : false
 
+  uart_is_16550:
+    datatype    : bool
+    description : Use 16550-compatible UART from OpenCores
+    paramtype   : generic
+    default     : true
+
+  has_uart1:
+    datatype    : bool
+    description : Enable second UART (always 16550-compatible)
+    paramtype   : generic
+    default     : false
+
   no_bram:
     datatype    : bool
     description : No internal block RAM (only DRAM and init code carrying payload)