- sim_console.vhdl
- logical.vhdl
- countzero.vhdl
- - gpr_hazard.vhdl
- - cr_hazard.vhdl
- control.vhdl
- execute1.vhdl
+ - fpu.vhdl
- loadstore1.vhdl
- mmu.vhdl
- dcache.vhdl
- - multiply.vhdl
- divider.vhdl
- rotator.vhdl
- writeback.vhdl
- fpga/firmware.hex : {copyto : firmware.hex, file_type : user}
file_type : vhdlSource-2008
+ xilinx_specific:
+ files:
+ - xilinx-mult.vhdl : {file_type : vhdlSource-2008}
+ - fpga/fpga-random.vhdl : {file_type : vhdlSource-2008}
+ - fpga/fpga-random.xdc : {file_type : xdc}
+
debug_xilinx:
files:
- dmi_dtm_xilinx.vhdl : {file_type : vhdlSource-2008}
- fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
- fpga/top-nexys-video.vhdl : {file_type : vhdlSource-2008}
+ acorn_cle_215:
+ files:
+ - fpga/acorn-cle-215.xdc : {file_type : xdc}
+ - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
+ - fpga/top-acorn-cle-215.vhdl : {file_type : vhdlSource-2008}
+
+ genesys2:
+ files:
+ - fpga/genesys2.xdc : {file_type : xdc}
+ - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
+ - fpga/top-genesys2.vhdl : {file_type : vhdlSource-2008}
+
arty_a7:
files:
- fpga/arty_a7.xdc : {file_type : xdc}
litedram:
depend : [":microwatt:litedram"]
+ liteeth:
+ depend : [":microwatt:liteeth"]
+
+ uart16550:
+ depend : ["::uart16550"]
+
targets:
nexys_a7:
default_tool: vivado
- filesets: [core, nexys_a7, soc, fpga, debug_xilinx]
+ filesets: [core, nexys_a7, soc, fpga, debug_xilinx, uart16550, xilinx_specific]
parameters :
- memory_size
- ram_init_file
- clk_input
- clk_frequency
- disable_flatten_core
+ - log_length=2048
+ - uart_is_16550
+ - has_fpu
+ - has_btc
tools:
vivado: {part : xc7a100tcsg324-1}
toplevel : toplevel
+ acorn-cle-215-nodram:
+ default_tool: vivado
+ filesets: [core, acorn_cle_215, soc, fpga, debug_xilinx, uart16550, xilinx_specific]
+ parameters :
+ - memory_size
+ - ram_init_file
+ - clk_input
+ - clk_frequency
+ - disable_flatten_core
+ - spi_flash_offset=10485760
+ - log_length=2048
+ - uart_is_16550
+ tools:
+ vivado: {part : xc7a200tsbg484-2}
+ toplevel : toplevel
+
+ genesys2-nodram:
+ default_tool: vivado
+ filesets: [core, genesys2, soc, fpga, debug_xilinx, uart16550, xilinx_specific]
+ parameters :
+ - memory_size
+ - ram_init_file
+ - clk_frequency
+ - use_litedram=false
+ - no_bram=false
+ - disable_flatten_core
+ - spi_flash_offset=10485760
+ - log_length=2048
+ - uart_is_16550=false
+ tools:
+ vivado: {part : xc7k325tffg900-2}
+ toplevel : toplevel
+
+ acorn-cle-215:
+ default_tool: vivado
+ filesets: [core, acorn_cle_215, soc, fpga, debug_xilinx, litedram, uart16550, xilinx_specific]
+ parameters :
+ - memory_size
+ - ram_init_file
+ - use_litedram=true
+ - disable_flatten_core
+ - no_bram
+ - spi_flash_offset=10485760
+ - log_length=2048
+ - uart_is_16550
+ generate: [litedram_acorn_cle_215]
+ tools:
+ vivado: {part : xc7a200tsbg484-2}
+ toplevel : toplevel
+
+ genesys2:
+ default_tool: vivado
+ filesets: [core, genesys2, soc, fpga, debug_xilinx, litedram, uart16550, xilinx_specific]
+ parameters :
+ - memory_size
+ - ram_init_file
+ - use_litedram=true
+ - disable_flatten_core
+ - no_bram
+ - spi_flash_offset=10485760
+ - log_length=2048
+ - uart_is_16550=false
+ generate: [litedram_genesys2]
+ tools:
+ vivado: {part : xc7k325tffg900-2}
+ toplevel : toplevel
+
nexys_video-nodram:
default_tool: vivado
- filesets: [core, nexys_video, soc, fpga, debug_xilinx]
+ filesets: [core, nexys_video, soc, fpga, debug_xilinx, uart16550, xilinx_specific]
parameters :
- memory_size
- ram_init_file
- clk_frequency
- disable_flatten_core
- spi_flash_offset=10485760
+ - log_length=2048
+ - uart_is_16550
+ - has_fpu
+ - has_btc
tools:
vivado: {part : xc7a200tsbg484-1}
toplevel : toplevel
nexys_video:
default_tool: vivado
- filesets: [core, nexys_video, soc, fpga, debug_xilinx, litedram]
+ filesets: [core, nexys_video, soc, fpga, debug_xilinx, litedram, uart16550, xilinx_specific]
parameters:
- memory_size
- ram_init_file
- disable_flatten_core
- no_bram
- spi_flash_offset=10485760
- generate: [dram_nexys_video]
+ - log_length=2048
+ - uart_is_16550
+ - has_fpu
+ - has_btc
+ generate: [litedram_nexys_video]
tools:
vivado: {part : xc7a200tsbg484-1}
toplevel : toplevel
arty_a7-35-nodram:
default_tool: vivado
- filesets: [core, arty_a7, soc, fpga, debug_xilinx]
+ filesets: [core, arty_a7, soc, fpga, debug_xilinx, uart16550, xilinx_specific]
parameters :
- memory_size
- ram_init_file
- clk_frequency
- disable_flatten_core
- spi_flash_offset=3145728
+ - log_length=512
+ - uart_is_16550
+ - has_uart1
+ - has_fpu=false
+ - has_btc=false
tools:
vivado: {part : xc7a35ticsg324-1L}
toplevel : toplevel
arty_a7-35:
default_tool: vivado
- filesets: [core, arty_a7, soc, fpga, debug_xilinx, litedram]
+ filesets: [core, arty_a7, soc, fpga, debug_xilinx, litedram, liteeth, uart16550, xilinx_specific]
parameters :
- memory_size
- ram_init_file
- use_litedram=true
+ - use_liteeth=true
- disable_flatten_core
- no_bram
- spi_flash_offset=3145728
- generate: [dram_arty]
+ - log_length=512
+ - uart_is_16550
+ - has_uart1
+ - has_fpu=false
+ - has_btc=false
+ generate: [litedram_arty, liteeth_arty]
tools:
vivado: {part : xc7a35ticsg324-1L}
toplevel : toplevel
arty_a7-100-nodram:
default_tool: vivado
- filesets: [core, arty_a7, soc, fpga, debug_xilinx]
+ filesets: [core, arty_a7, soc, fpga, debug_xilinx, uart16550, xilinx_specific]
parameters :
- memory_size
- ram_init_file
- clk_frequency
- disable_flatten_core
- spi_flash_offset=4194304
+ - log_length=2048
+ - uart_is_16550
+ - has_uart1
+ - has_fpu
+ - has_btc
tools:
vivado: {part : xc7a100ticsg324-1L}
toplevel : toplevel
arty_a7-100:
default_tool: vivado
- filesets: [core, arty_a7, soc, fpga, debug_xilinx, litedram]
+ filesets: [core, arty_a7, soc, fpga, debug_xilinx, litedram, liteeth, uart16550, xilinx_specific]
parameters:
- memory_size
- ram_init_file
- use_litedram=true
+ - use_liteeth=true
- disable_flatten_core
- no_bram
- spi_flash_offset=4194304
- generate: [dram_arty]
+ - log_length=2048
+ - uart_is_16550
+ - has_uart1
+ - has_fpu
+ - has_btc
+ generate: [litedram_arty, liteeth_arty]
tools:
vivado: {part : xc7a100ticsg324-1L}
toplevel : toplevel
cmod_a7-35:
default_tool: vivado
- filesets: [core, cmod_a7-35, soc, fpga, debug_xilinx]
+ filesets: [core, cmod_a7-35, soc, fpga, debug_xilinx, uart16550, xilinx_specific]
parameters :
- memory_size
- ram_init_file
- clk_input=12000000
- clk_frequency
- disable_flatten_core
+ - log_length=512
+ - uart_is_16550
+ - has_fpu=false
+ - has_btc=false
tools:
vivado: {part : xc7a35tcpg236-1}
toplevel : toplevel
synth:
- filesets: [core, soc]
+ filesets: [core, soc, xilinx_specific]
tools:
vivado: {pnr : none}
toplevel: core
generate:
- dram_arty:
+ litedram_arty:
generator: litedram_gen
parameters: {board : arty}
- dram_nexys_video:
+ liteeth_arty:
+ generator: liteeth_gen
+ parameters: {board : arty}
+
+ litedram_nexys_video:
generator: litedram_gen
parameters: {board : nexys-video}
+ litedram_acorn_cle_215:
+ generator: litedram_gen
+ parameters: {board : acorn-cle-215}
+
+ litedram_genesys2:
+ generator: litedram_gen
+ parameters: {board : genesys2}
+
parameters:
memory_size:
datatype : int
paramtype : generic
default : 100000000
+ has_fpu:
+ datatype : bool
+ description : Include a floating-point unit in the core
+ paramtype : generic
+ default : true
+
+ has_btc:
+ datatype : bool
+ description : Include a branch target cache in the core
+ paramtype : generic
+ default : true
+
disable_flatten_core:
datatype : bool
description : Prevent Vivado from flattening the main core components
paramtype : generic
default : false
+ use_liteeth:
+ datatype : bool
+ description : Use liteEth
+ paramtype : generic
+ default : false
+
+ uart_is_16550:
+ datatype : bool
+ description : Use 16550-compatible UART from OpenCores
+ paramtype : generic
+ default : true
+
+ has_uart1:
+ datatype : bool
+ description : Enable second UART (always 16550-compatible)
+ paramtype : generic
+ default : false
+
no_bram:
datatype : bool
description : No internal block RAM (only DRAM and init code carrying payload)
datatype : int
description : Offset (in bytes) in the SPI flash of the code payload to run
paramtype : generic
+
+ log_length:
+ datatype : int
+ description : Length of the core log buffer in entries (32 bytes each)
+ paramtype : generic