- sim_console.vhdl
- logical.vhdl
- countzero.vhdl
- - gpr_hazard.vhdl
- - cr_hazard.vhdl
- control.vhdl
- execute1.vhdl
+ - fpu.vhdl
- loadstore1.vhdl
- mmu.vhdl
- dcache.vhdl
xilinx_specific:
files:
- xilinx-mult.vhdl : {file_type : vhdlSource-2008}
+ - fpga/fpga-random.vhdl : {file_type : vhdlSource-2008}
+ - fpga/fpga-random.xdc : {file_type : xdc}
debug_xilinx:
files:
- disable_flatten_core
- log_length=2048
- uart_is_16550
+ - has_fpu
+ - has_btc
tools:
vivado: {part : xc7a100tcsg324-1}
toplevel : toplevel
- spi_flash_offset=10485760
- log_length=2048
- uart_is_16550
+ - has_fpu
+ - has_btc
tools:
vivado: {part : xc7a200tsbg484-1}
toplevel : toplevel
- spi_flash_offset=10485760
- log_length=2048
- uart_is_16550
+ - has_fpu
+ - has_btc
generate: [litedram_nexys_video]
tools:
vivado: {part : xc7a200tsbg484-1}
- log_length=512
- uart_is_16550
- has_uart1
+ - has_fpu=false
+ - has_btc=false
tools:
vivado: {part : xc7a35ticsg324-1L}
toplevel : toplevel
- log_length=512
- uart_is_16550
- has_uart1
+ - has_fpu=false
+ - has_btc=false
generate: [litedram_arty, liteeth_arty]
tools:
vivado: {part : xc7a35ticsg324-1L}
- log_length=2048
- uart_is_16550
- has_uart1
+ - has_fpu
+ - has_btc
tools:
vivado: {part : xc7a100ticsg324-1L}
toplevel : toplevel
- log_length=2048
- uart_is_16550
- has_uart1
+ - has_fpu
+ - has_btc
generate: [litedram_arty, liteeth_arty]
tools:
vivado: {part : xc7a100ticsg324-1L}
- disable_flatten_core
- log_length=512
- uart_is_16550
+ - has_fpu=false
+ - has_btc=false
tools:
vivado: {part : xc7a35tcpg236-1}
toplevel : toplevel
paramtype : generic
default : 100000000
+ has_fpu:
+ datatype : bool
+ description : Include a floating-point unit in the core
+ paramtype : generic
+ default : true
+
+ has_btc:
+ datatype : bool
+ description : Include a branch target cache in the core
+ paramtype : generic
+ default : true
+
disable_flatten_core:
datatype : bool
description : Prevent Vivado from flattening the main core components