build.plat: TemplatedPlatform.iter_extra_files→Platform.iter_files.

[nmigen.git] / nmigen / vendor / lattice_ice40.py

diff --git a/nmigen/vendor/lattice_ice40.py b/nmigen/vendor/lattice_ice40.py
index 4e6b2820fe1b8e890127796095e684fb06dc9d14..c9c35b353096b509b743ebd5f807cc9533dd105c 100644 (file)
--- a/nmigen/vendor/lattice_ice40.py
+++ b/nmigen/vendor/lattice_ice40.py
@@ -114,13 +114,13 @@ class LatticeICE40Platform(TemplatedPlatform):
         """,
         "{{name}}.ys": r"""
             # {{autogenerated}}
-            {% for file in platform.iter_extra_files(".v") -%}
+            {% for file in platform.iter_files(".v") -%}
                 read_verilog {{get_override("read_verilog_opts")|options}} {{file}}
             {% endfor %}
-            {% for file in platform.iter_extra_files(".sv") -%}
+            {% for file in platform.iter_files(".sv") -%}
                 read_verilog -sv {{get_override("read_verilog_opts")|options}} {{file}}
             {% endfor %}
-            {% for file in platform.iter_extra_files(".il") -%}
+            {% for file in platform.iter_files(".il") -%}
                 read_ilang {{file}}
             {% endfor %}
             read_ilang {{name}}.il
@@ -212,7 +212,7 @@ class LatticeICE40Platform(TemplatedPlatform):
             -d {{platform.device}}
             -t {{platform.package}}
             {{get_override("lse_opts")|options|default("# (lse_opts placeholder)")}}
-            {% for file in platform.iter_extra_files(".v") -%}
+            {% for file in platform.iter_files(".v") -%}
                 -ver {{file}}
             {% endfor %}
             -ver {{name}}.v
@@ -223,7 +223,7 @@ class LatticeICE40Platform(TemplatedPlatform):
         """,
         "{{name}}_syn.prj": r"""
             # {{autogenerated}}
-            {% for file in platform.iter_extra_files(".v", ".sv", ".vhd", ".vhdl") -%}
+            {% for file in platform.iter_files(".v", ".sv", ".vhd", ".vhdl") -%}
                 add_file -verilog {{file|tcl_escape}}
             {% endfor %}
             add_file -verilog {{name}}.v