wishbone: fix docstring & unneeded parameter for InterconnectShared

[nmigen-soc.git] / nmigen_soc / wishbone / sram.py

diff --git a/nmigen_soc/wishbone/sram.py b/nmigen_soc/wishbone/sram.py
index b72687dd544a80f7b4dcb5149ed930b5b000a7e4..84faeeda80f7d98b68e6d1565e380e5be1397e23 100644 (file)
--- a/nmigen_soc/wishbone/sram.py
+++ b/nmigen_soc/wishbone/sram.py
@@ -8,16 +8,46 @@ __all__ = ["SRAM"]
 
 
 class SRAM(Elaboratable):
+    """SRAM module carrying a volatile memory block (implemented with :class:`Memory`)
+    that can be read and write (or only read if the SRAM is read-only) through a Wishbone bus.
+
+    If no Wishbone bus is specified during initialisation, this creates one whose address width
+    is just enough to fit the whole memory (i.e. equals to the log2(memory depth) rounded up), and
+    whose data width is equal to the memory width.
+
+    Parameters
+    ----------
+    memory : :class:`Memory`
+        The memory to be accessed via the Wishbone bus.
+    read_only : bool
+        Whether or not the memory is read-only. Defaults to False.
+    bus : :class:`Interface` or None
+        The Wishbone bus interface providing access to the read/write ports of the memory.
+        Optional and defaults to None, which lets this module to instantiate one as described
+        above, having the granularity, features and alignment as specified by their
+        corresponding parameters.
+    granularity : int or None
+        If the Wishbone bus is not sepcified, this is the granularity of the Wishbone bus.
+        Optional. See :class:`Interface`.
+    features : iter(str)
+        If the Wishbone bus is not sepcified, this is the optional signal set for the Wishbone bus.
+        See :class:`Interface`.
+
+    Attributes
+    ----------
+    memory : :class:`Memory`
+        The memory to be accessed via the Wishbone bus.
+    bus : :class:`Interface`
+        The Wishbone bus interface providing access to the read/write ports of the memory.
     """
-    """
-    def __init__(self, memory, read_only=False, bus=None, 
+    def __init__(self, memory, read_only=False, bus=None,
                  granularity=None, features=frozenset()):
         if not isinstance(memory, Memory):
             raise TypeError("Memory {!r} is not a Memory"
                             .format(memory))
         self.memory = memory
         self.read_only = read_only
-        # Define total address space: 
+        # Define total address space:
         # - Base: equals memory.depth
         # - Has an additional ReadPort: add rdport.depth
         # - Has an additional WirtePort: add wrport.depth
@@ -39,7 +69,7 @@ class SRAM(Elaboratable):
 
         if self.memory.width > len(self.bus.dat_r):
             raise NotImplementedError
-    
+
         # read
         m.submodules.rdport = rdport = self.memory.read_port()
         m.d.comb += [
@@ -55,7 +85,8 @@ class SRAM(Elaboratable):
                 wrport.data.eq(self.bus.dat_w)
             ]
             for i in range(4):
-                m.d.comb += wrport.en[i].eq(self.bus.cyc & self.bus.stb & self.bus.we & self.bus.sel[i])
+                m.d.comb += wrport.en[i].eq(self.bus.cyc & self.bus.stb &
+                                            self.bus.we & self.bus.sel[i])
 
         # generate ack
         m.d.sync += self.bus.ack.eq(0)