Add Tercel PHY reset synchronization

[microwatt.git] / plru.vhdl

diff --git a/plru.vhdl b/plru.vhdl
index 6907c2bc82d2ca55bf856039d33bc3249aa6a184..6caa2efc4dd5ac3deb8e21628877abb0d152f58a 100644 (file)
--- a/plru.vhdl
+++ b/plru.vhdl
@@ -29,7 +29,7 @@ begin
     -- XXX Check if we can turn that into a little ROM instead that
     -- takes the tree bit vector and returns the LRU. See if it's better
     -- in term of FPGA resouces usage...
-    get_lru: process(all)
+    get_lru: process(tree)
        variable node : node_t;
     begin
        node := 0;