get arty a7-100t functional

[libresoc-litex.git] / sim.py

diff --git a/sim.py b/sim.py
index 44fcf1b5da8936dc254d39fc740a6ee2d17b17d9..f4ec8dce544e5ede1ec909d86cd28a7b3d2df08b 100755 (executable)
--- a/sim.py
+++ b/sim.py
@@ -59,10 +59,10 @@ class LibreSoCSim(SoCSDRAM):
         #ram_fname = "/tmp/test.bin"
         #ram_fname = "/home/lkcl/src/libresoc/microwatt/" \
         #            "micropython/firmware.bin"
-        #ram_fname = "/home/lkcl/src/libresoc/microwatt/" \
-        #            "tests/xics/xics.bin"
         ram_fname = "/home/lkcl/src/libresoc/microwatt/" \
-                    "tests/decrementer/decrementer.bin"
+                    "tests/xics/xics.bin"
+        #ram_fname = "/home/lkcl/src/libresoc/microwatt/" \
+        #            "tests/decrementer/decrementer.bin"
         #ram_fname = "/home/lkcl/src/libresoc/microwatt/" \
         #            "hello_world/hello_world.bin"
         ram_fname = "/home/lkcl/src/libresoc/microwatt/" \