CLK_FREQ : positive;
SIM : boolean;
HAS_FPU : boolean := true;
+ HAS_BTC : boolean := true;
DISABLE_FLATTEN_CORE : boolean := false;
HAS_DRAM : boolean := false;
DRAM_SIZE : integer := 0;
SPI_FLASH_OFFSET : integer := 0;
SPI_FLASH_DEF_CKDV : natural := 2;
SPI_FLASH_DEF_QUAD : boolean := false;
+ SPI_BOOT_CLOCKS : boolean := true;
LOG_LENGTH : natural := 512;
HAS_LITEETH : boolean := false;
+ HAS_TERCEL : boolean := false;
+ HAS_LPC_SLAVE : boolean := false;
UART0_IS_16550 : boolean := true;
- HAS_UART1 : boolean := false
+ HAS_UART1 : boolean := false;
+ ICACHE_NUM_LINES : natural := 64;
+ ICACHE_NUM_WAYS : natural := 2;
+ ICACHE_TLB_SIZE : natural := 64;
+ DCACHE_NUM_LINES : natural := 64;
+ DCACHE_NUM_WAYS : natural := 2;
+ DCACHE_TLB_SET_SIZE : natural := 64;
+ DCACHE_TLB_NUM_WAYS : natural := 2
);
port(
rst : in std_ulogic;
wb_ext_is_dram_csr : out std_ulogic;
wb_ext_is_dram_init : out std_ulogic;
wb_ext_is_eth : out std_ulogic;
+ wb_ext_is_tercel : out std_ulogic;
+ wb_ext_is_lpc_slave : out std_ulogic;
-- External interrupts
ext_irq_eth : in std_ulogic := '0';
uart1_txd : out std_ulogic;
uart1_rxd : in std_ulogic := '0';
- -- SPI Flash signals
- spi_flash_sck : out std_ulogic;
- spi_flash_cs_n : out std_ulogic;
- spi_flash_sdat_o : out std_ulogic_vector(SPI_FLASH_DLINES-1 downto 0);
- spi_flash_sdat_oe : out std_ulogic_vector(SPI_FLASH_DLINES-1 downto 0);
- spi_flash_sdat_i : in std_ulogic_vector(SPI_FLASH_DLINES-1 downto 0) := (others => '1');
+ -- SPI Flash controller signals:
+ wb_spiflash_in : out wb_io_master_out;
+ wb_spiflash_out : in wb_io_slave_out := wb_io_slave_out_init;
+
+ -- LPC slave DMA signals
+ wb_lpc_slave_in : out wishbone_slave_out;
+ wb_lpc_slave_out : in wishbone_master_out;
-- DRAM controller signals
alt_reset : in std_ulogic := '0'
signal wishbone_icore_out : wishbone_master_out;
signal wishbone_debug_in : wishbone_slave_out;
signal wishbone_debug_out : wishbone_master_out;
+ signal wishbone_lpc_in : wishbone_slave_out;
+ signal wishbone_lpc_out : wishbone_master_out;
-- Arbiter array (ghdl doesnt' support assigning the array
-- elements in the entity instantiation)
- constant NUM_WB_MASTERS : positive := 3;
+ constant NUM_WB_MASTERS : positive := 4;
signal wb_masters_out : wishbone_master_out_vector(0 to NUM_WB_MASTERS-1);
signal wb_masters_in : wishbone_slave_out_vector(0 to NUM_WB_MASTERS-1);
signal uart1_dat8 : std_ulogic_vector(7 downto 0);
signal uart1_irq : std_ulogic;
- -- SPI Flash controller signals:
- signal wb_spiflash_in : wb_io_master_out;
- signal wb_spiflash_out : wb_io_slave_out;
- signal wb_spiflash_is_reg : std_ulogic;
- signal wb_spiflash_is_map : std_ulogic;
-
-- XICS signals:
signal wb_xics_icp_in : wb_io_master_out;
signal wb_xics_icp_out : wb_io_slave_out;
SLAVE_IO_ICP,
SLAVE_IO_ICS,
SLAVE_IO_UART1,
- SLAVE_IO_SPI_FLASH_REG,
SLAVE_IO_SPI_FLASH_MAP,
SLAVE_IO_EXTERNAL,
SLAVE_IO_NONE);
generic map(
SIM => SIM,
HAS_FPU => HAS_FPU,
+ HAS_BTC => HAS_BTC,
DISABLE_FLATTEN => DISABLE_FLATTEN_CORE,
ALT_RESET_ADDRESS => (23 downto 0 => '0', others => '1'),
- LOG_LENGTH => LOG_LENGTH
+ LOG_LENGTH => LOG_LENGTH,
+ ICACHE_NUM_LINES => ICACHE_NUM_LINES,
+ ICACHE_NUM_WAYS => ICACHE_NUM_WAYS,
+ ICACHE_TLB_SIZE => ICACHE_TLB_SIZE,
+ DCACHE_NUM_LINES => DCACHE_NUM_LINES,
+ DCACHE_NUM_WAYS => DCACHE_NUM_WAYS,
+ DCACHE_TLB_SET_SIZE => DCACHE_TLB_SET_SIZE,
+ DCACHE_TLB_NUM_WAYS => DCACHE_TLB_NUM_WAYS
)
port map(
clk => system_clk,
-- Wishbone bus master arbiter & mux
wb_masters_out <= (0 => wishbone_dcore_out,
1 => wishbone_icore_out,
- 2 => wishbone_debug_out);
+ 2 => wishbone_debug_out,
+ 3 => wishbone_lpc_out);
wishbone_dcore_in <= wb_masters_in(0);
wishbone_icore_in <= wb_masters_in(1);
wishbone_debug_in <= wb_masters_in(2);
+ wishbone_lpc_in <= wb_masters_in(3);
wishbone_arbiter_0: entity work.wishbone_arbiter
generic map(
NUM_MASTERS => NUM_WB_MASTERS
slave_io := SLAVE_IO_ICP;
elsif std_match(match, x"C0005") then
slave_io := SLAVE_IO_ICS;
- elsif std_match(match, x"C0006") then
- slave_io := SLAVE_IO_SPI_FLASH_REG;
end if;
slave_io_dbg <= slave_io;
wb_uart0_in <= wb_sio_out;
wb_uart1_in.cyc <= '0';
wb_spiflash_in <= wb_sio_out;
wb_spiflash_in.cyc <= '0';
- wb_spiflash_is_reg <= '0';
- wb_spiflash_is_map <= '0';
-- Only give xics 8 bits of wb addr (for now...)
wb_xics_icp_in <= wb_sio_out;
elsif wb_sio_out.adr(23 downto 16) = x"03" and HAS_LITEETH then
wb_ext_is_eth <= '1';
ext_valid := true;
+ elsif wb_sio_out.adr(21 downto 14) = x"04" and HAS_LPC_SLAVE then
+ wb_ext_is_lpc_slave <= '1';
+ ext_valid := true;
+ elsif wb_sio_out.adr(21 downto 14) = x"05" and HAS_TERCEL then
+ wb_ext_is_tercel <= '1';
+ ext_valid := true;
end if;
if ext_valid then
wb_ext_io_in.cyc <= wb_sio_out.cyc;
wb_spiflash_in.adr(29 downto 28) <= "00";
wb_spiflash_in.cyc <= wb_sio_out.cyc;
wb_sio_in <= wb_spiflash_out;
- wb_spiflash_is_map <= '1';
- when SLAVE_IO_SPI_FLASH_REG =>
- wb_spiflash_in.cyc <= wb_sio_out.cyc;
- wb_sio_in <= wb_spiflash_out;
- wb_spiflash_is_reg <= '1';
when others =>
end case;
wb_uart1_out.dat <= x"00000000";
wb_uart1_out.ack <= wb_uart1_in.cyc and wb_uart1_in.stb;
wb_uart1_out.stall <= '0';
- end generate;
-
- spiflash_gen: if HAS_SPI_FLASH generate
- spiflash: entity work.spi_flash_ctrl
- generic map (
- DATA_LINES => SPI_FLASH_DLINES,
- DEF_CLK_DIV => SPI_FLASH_DEF_CKDV,
- DEF_QUAD_READ => SPI_FLASH_DEF_QUAD
- )
- port map(
- rst => rst_spi,
- clk => system_clk,
- wb_in => wb_spiflash_in,
- wb_out => wb_spiflash_out,
- wb_sel_reg => wb_spiflash_is_reg,
- wb_sel_map => wb_spiflash_is_map,
- sck => spi_flash_sck,
- cs_n => spi_flash_cs_n,
- sdat_o => spi_flash_sdat_o,
- sdat_oe => spi_flash_sdat_oe,
- sdat_i => spi_flash_sdat_i
- );
- end generate;
-
- no_spi0_gen: if not HAS_SPI_FLASH generate
- wb_spiflash_out.dat <= (others => '1');
- wb_spiflash_out.ack <= wb_spiflash_in.cyc and wb_spiflash_in.stb;
- wb_spiflash_out.stall <= wb_spiflash_in.cyc and not wb_spiflash_out.ack;
+ uart1_irq <= '0';
end generate;
xics_icp: entity work.xics_icp
wb_in => wishbone_debug_in,
wb_out => wishbone_debug_out);
+--pragma synthesis_off
+ wb_x_state: process(system_clk)
+ begin
+ if rising_edge(system_clk) then
+ if not rst then
+ -- Wishbone arbiter
+ assert not(is_x(wb_masters_out(0).cyc)) and not(is_x(wb_masters_out(0).stb)) severity failure;
+ assert not(is_x(wb_masters_out(1).cyc)) and not(is_x(wb_masters_out(1).stb)) severity failure;
+ assert not(is_x(wb_masters_out(2).cyc)) and not(is_x(wb_masters_out(2).stb)) severity failure;
+ assert not(is_x(wb_masters_out(3).cyc)) and not(is_x(wb_masters_out(3).stb)) severity failure;
+ assert not(is_x(wb_masters_in(0).ack)) severity failure;
+ assert not(is_x(wb_masters_in(1).ack)) severity failure;
+ assert not(is_x(wb_masters_in(2).ack)) severity failure;
+ assert not(is_x(wb_masters_in(3).ack)) severity failure;
+
+ -- Main memory wishbones
+ assert not(is_x(wb_bram_in.cyc)) and not (is_x(wb_bram_in.stb)) severity failure;
+ assert not(is_x(wb_dram_in.cyc)) and not (is_x(wb_dram_in.stb)) severity failure;
+ assert not(is_x(wb_io_in.cyc)) and not (is_x(wb_io_in.stb)) severity failure;
+ assert not(is_x(wb_bram_out.ack)) severity failure;
+ assert not(is_x(wb_dram_out.ack)) severity failure;
+ assert not(is_x(wb_io_out.ack)) severity failure;
+
+ -- I/O wishbones
+ assert not(is_x(wb_uart0_in.cyc)) and not(is_x(wb_uart0_in.stb)) severity failure;
+ assert not(is_x(wb_uart1_in.cyc)) and not(is_x(wb_uart1_in.stb)) severity failure;
+ assert not(is_x(wb_spiflash_in.cyc)) and not(is_x(wb_spiflash_in.stb)) severity failure;
+ assert not(is_x(wb_xics_icp_in.cyc)) and not(is_x(wb_xics_icp_in.stb)) severity failure;
+ assert not(is_x(wb_xics_ics_in.cyc)) and not(is_x(wb_xics_ics_in.stb)) severity failure;
+ assert not(is_x(wb_ext_io_in.cyc)) and not(is_x(wb_ext_io_in.stb)) severity failure;
+ assert not(is_x(wb_syscon_in.cyc)) and not(is_x(wb_syscon_in.stb)) severity failure;
+ assert not(is_x(wb_uart0_out.ack)) severity failure;
+ assert not(is_x(wb_uart1_out.ack)) severity failure;
+ assert not(is_x(wb_spiflash_out.ack)) severity failure;
+ assert not(is_x(wb_xics_icp_out.ack)) severity failure;
+ assert not(is_x(wb_xics_ics_out.ack)) severity failure;
+ assert not(is_x(wb_ext_io_out.ack)) severity failure;
+ assert not(is_x(wb_syscon_out.ack)) severity failure;
+ end if;
+ end if;
+ end process;
+--pragma synthesis_on
+
+ -- LPC slave DMA
+ wb_lpc_slave_in <= wishbone_lpc_in;
+ wishbone_lpc_out <= wb_lpc_slave_out;
end architecture behaviour;
projects / microwatt.git / blobdiff