-- IO Bus:
-- 0xc0000000: SYSCON
-- 0xc0002000: UART0
+-- 0xc0003000: UART1 (if any)
-- 0xc0004000: XICS ICP
+-- 0xc0005000: XICS ICS
-- 0xc0006000: SPI Flash controller
-- 0xc8nnnnnn: External IO bus
-- 0xf0000000: Flash "ROM" mapping
-- External IO bus:
-- 0xc8000000: LiteDRAM control (CSRs)
+-- 0xc8020000: LiteEth CSRs (*)
+-- 0xc8030000: LiteEth MMIO (*)
+
+-- (*) LiteEth must be a single aligned 32KB block as the CSRs and MMIOs
+-- are actually decoded as a single wishbone which LiteEth will
+-- internally split based on bit 16.
-- (**) DRAM init code is currently special and goes to the external
-- IO bus, this will be fixed when it's moved out of litedram and
-- into the main SoC once we have a common "firmware".
+-- Interrupt numbers:
+--
+-- 0 : UART0
+-- 1 : Ethernet
entity soc is
generic (
RAM_INIT_FILE : string;
CLK_FREQ : positive;
SIM : boolean;
+ HAS_FPU : boolean := true;
+ HAS_BTC : boolean := true;
DISABLE_FLATTEN_CORE : boolean := false;
HAS_DRAM : boolean := false;
DRAM_SIZE : integer := 0;
SPI_FLASH_DLINES : positive := 1;
SPI_FLASH_OFFSET : integer := 0;
SPI_FLASH_DEF_CKDV : natural := 2;
- SPI_FLASH_DEF_QUAD : boolean := false
+ SPI_FLASH_DEF_QUAD : boolean := false;
+ SPI_BOOT_CLOCKS : boolean := true;
+ LOG_LENGTH : natural := 512;
+ HAS_LITEETH : boolean := false;
+ HAS_TERCEL : boolean := false;
+ HAS_LPC_SLAVE : boolean := false;
+ UART0_IS_16550 : boolean := true;
+ HAS_UART1 : boolean := false;
+ ICACHE_NUM_LINES : natural := 64;
+ ICACHE_NUM_WAYS : natural := 2;
+ ICACHE_TLB_SIZE : natural := 64;
+ DCACHE_NUM_LINES : natural := 64;
+ DCACHE_NUM_WAYS : natural := 2;
+ DCACHE_TLB_SET_SIZE : natural := 64;
+ DCACHE_TLB_NUM_WAYS : natural := 2
);
port(
rst : in std_ulogic;
wb_ext_io_out : in wb_io_slave_out := wb_io_slave_out_init;
wb_ext_is_dram_csr : out std_ulogic;
wb_ext_is_dram_init : out std_ulogic;
+ wb_ext_is_eth : out std_ulogic;
+ wb_ext_is_tercel : out std_ulogic;
+ wb_ext_is_lpc_slave : out std_ulogic;
+
+ -- External interrupts
+ ext_irq_eth : in std_ulogic := '0';
-- UART0 signals:
uart0_txd : out std_ulogic;
uart0_rxd : in std_ulogic := '0';
- -- SPI Flash signals
- spi_flash_sck : out std_ulogic;
- spi_flash_cs_n : out std_ulogic;
- spi_flash_sdat_o : out std_ulogic_vector(SPI_FLASH_DLINES-1 downto 0);
- spi_flash_sdat_oe : out std_ulogic_vector(SPI_FLASH_DLINES-1 downto 0);
- spi_flash_sdat_i : in std_ulogic_vector(SPI_FLASH_DLINES-1 downto 0) := (others => '1');
+ -- UART1 signals:
+ uart1_txd : out std_ulogic;
+ uart1_rxd : in std_ulogic := '0';
+
+ -- SPI Flash controller signals:
+ wb_spiflash_in : out wb_io_master_out;
+ wb_spiflash_out : in wb_io_slave_out := wb_io_slave_out_init;
+
+ -- LPC slave DMA signals
+ wb_lpc_slave_in : out wishbone_slave_out;
+ wb_lpc_slave_out : in wishbone_master_out;
-- DRAM controller signals
alt_reset : in std_ulogic := '0'
signal wishbone_icore_out : wishbone_master_out;
signal wishbone_debug_in : wishbone_slave_out;
signal wishbone_debug_out : wishbone_master_out;
+ signal wishbone_lpc_in : wishbone_slave_out;
+ signal wishbone_lpc_out : wishbone_master_out;
-- Arbiter array (ghdl doesnt' support assigning the array
-- elements in the entity instantiation)
- constant NUM_WB_MASTERS : positive := 3;
+ constant NUM_WB_MASTERS : positive := 4;
signal wb_masters_out : wishbone_master_out_vector(0 to NUM_WB_MASTERS-1);
signal wb_masters_in : wishbone_slave_out_vector(0 to NUM_WB_MASTERS-1);
-- UART0 signals:
signal wb_uart0_in : wb_io_master_out;
signal wb_uart0_out : wb_io_slave_out;
- signal uart_dat8 : std_ulogic_vector(7 downto 0);
-
- -- SPI Flash controller signals:
- signal wb_spiflash_in : wb_io_master_out;
- signal wb_spiflash_out : wb_io_slave_out;
- signal wb_spiflash_is_reg : std_ulogic;
- signal wb_spiflash_is_map : std_ulogic;
-
- -- XICS0 signals:
- signal wb_xics0_in : wb_io_master_out;
- signal wb_xics0_out : wb_io_slave_out;
- signal int_level_in : std_ulogic_vector(15 downto 0);
-
- signal core_ext_irq : std_ulogic;
+ signal uart0_dat8 : std_ulogic_vector(7 downto 0);
+ signal uart0_irq : std_ulogic;
+
+ -- UART1 signals:
+ signal wb_uart1_in : wb_io_master_out;
+ signal wb_uart1_out : wb_io_slave_out;
+ signal uart1_dat8 : std_ulogic_vector(7 downto 0);
+ signal uart1_irq : std_ulogic;
+
+ -- XICS signals:
+ signal wb_xics_icp_in : wb_io_master_out;
+ signal wb_xics_icp_out : wb_io_slave_out;
+ signal wb_xics_ics_in : wb_io_master_out;
+ signal wb_xics_ics_out : wb_io_slave_out;
+ signal int_level_in : std_ulogic_vector(15 downto 0);
+ signal ics_to_icp : ics_to_icp_t;
+ signal core_ext_irq : std_ulogic;
-- Main memory signals:
signal wb_bram_in : wishbone_master_out;
-- IO branch split:
type slave_io_type is (SLAVE_IO_SYSCON,
SLAVE_IO_UART,
- SLAVE_IO_ICP_0,
- SLAVE_IO_SPI_FLASH_REG,
+ SLAVE_IO_ICP,
+ SLAVE_IO_ICS,
+ SLAVE_IO_UART1,
SLAVE_IO_SPI_FLASH_MAP,
SLAVE_IO_EXTERNAL,
SLAVE_IO_NONE);
signal slave_io_dbg : slave_io_type;
+
+ -- This is the component exported by the 16550 compatible
+ -- UART from FuseSoC.
+ --
+ component uart_top port (
+ wb_clk_i : in std_ulogic;
+ wb_rst_i : in std_ulogic;
+ wb_adr_i : in std_ulogic_vector(2 downto 0);
+ wb_dat_i : in std_ulogic_vector(7 downto 0);
+ wb_dat_o : out std_ulogic_vector(7 downto 0);
+ wb_we_i : in std_ulogic;
+ wb_stb_i : in std_ulogic;
+ wb_cyc_i : in std_ulogic;
+ wb_ack_o : out std_ulogic;
+ int_o : out std_ulogic;
+ stx_pad_o : out std_ulogic;
+ srx_pad_i : in std_ulogic;
+ rts_pad_o : out std_ulogic;
+ cts_pad_i : in std_ulogic;
+ dtr_pad_o : out std_ulogic;
+ dsr_pad_i : in std_ulogic;
+ ri_pad_i : in std_ulogic;
+ dcd_pad_i : in std_ulogic
+ );
+ end component;
begin
resets: process(system_clk)
processor: entity work.core
generic map(
SIM => SIM,
+ HAS_FPU => HAS_FPU,
+ HAS_BTC => HAS_BTC,
DISABLE_FLATTEN => DISABLE_FLATTEN_CORE,
- ALT_RESET_ADDRESS => (23 downto 0 => '0', others => '1')
+ ALT_RESET_ADDRESS => (23 downto 0 => '0', others => '1'),
+ LOG_LENGTH => LOG_LENGTH,
+ ICACHE_NUM_LINES => ICACHE_NUM_LINES,
+ ICACHE_NUM_WAYS => ICACHE_NUM_WAYS,
+ ICACHE_TLB_SIZE => ICACHE_TLB_SIZE,
+ DCACHE_NUM_LINES => DCACHE_NUM_LINES,
+ DCACHE_NUM_WAYS => DCACHE_NUM_WAYS,
+ DCACHE_TLB_SET_SIZE => DCACHE_TLB_SET_SIZE,
+ DCACHE_TLB_NUM_WAYS => DCACHE_TLB_NUM_WAYS
)
port map(
clk => system_clk,
-- Wishbone bus master arbiter & mux
wb_masters_out <= (0 => wishbone_dcore_out,
1 => wishbone_icore_out,
- 2 => wishbone_debug_out);
+ 2 => wishbone_debug_out,
+ 3 => wishbone_lpc_out);
wishbone_dcore_in <= wb_masters_in(0);
wishbone_icore_in <= wb_masters_in(1);
wishbone_debug_in <= wb_masters_in(2);
+ wishbone_lpc_in <= wb_masters_in(3);
wishbone_arbiter_0: entity work.wishbone_arbiter
generic map(
NUM_MASTERS => NUM_WB_MASTERS
wb_io_in.cyc <= wb_master_out.cyc;
wb_master_in <= wb_io_out;
end case;
+
end process slave_top_intercon;
-- IO wishbone slave 64->32 bits converter
-- IO wishbone slave intercon.
--
- slave_io_intercon: process(wb_sio_out, wb_syscon_out, wb_uart0_out,
- wb_ext_io_out, wb_xics0_out, wb_spiflash_out)
+ slave_io_intercon: process(wb_sio_out, wb_syscon_out, wb_uart0_out, wb_uart1_out,
+ wb_ext_io_out, wb_xics_icp_out, wb_xics_ics_out,
+ wb_spiflash_out)
variable slave_io : slave_io_type;
variable match : std_ulogic_vector(31 downto 12);
slave_io := SLAVE_IO_SYSCON;
elsif std_match(match, x"C0002") then
slave_io := SLAVE_IO_UART;
+ elsif std_match(match, x"C0003") then
+ slave_io := SLAVE_IO_UART1;
elsif std_match(match, x"C8---") then
slave_io := SLAVE_IO_EXTERNAL;
elsif std_match(match, x"C0004") then
- slave_io := SLAVE_IO_ICP_0;
- elsif std_match(match, x"C0006") then
- slave_io := SLAVE_IO_SPI_FLASH_REG;
+ slave_io := SLAVE_IO_ICP;
+ elsif std_match(match, x"C0005") then
+ slave_io := SLAVE_IO_ICS;
end if;
slave_io_dbg <= slave_io;
wb_uart0_in <= wb_sio_out;
wb_uart0_in.cyc <= '0';
+ wb_uart1_in <= wb_sio_out;
+ wb_uart1_in.cyc <= '0';
wb_spiflash_in <= wb_sio_out;
wb_spiflash_in.cyc <= '0';
- wb_spiflash_is_reg <= '0';
- wb_spiflash_is_map <= '0';
- -- Only give xics 8 bits of wb addr
- wb_xics0_in <= wb_sio_out;
- wb_xics0_in.adr <= (others => '0');
- wb_xics0_in.adr(7 downto 0) <= wb_sio_out.adr(7 downto 0);
- wb_xics0_in.cyc <= '0';
+ -- Only give xics 8 bits of wb addr (for now...)
+ wb_xics_icp_in <= wb_sio_out;
+ wb_xics_icp_in.adr <= (others => '0');
+ wb_xics_icp_in.adr(7 downto 0) <= wb_sio_out.adr(7 downto 0);
+ wb_xics_icp_in.cyc <= '0';
+ wb_xics_ics_in <= wb_sio_out;
+ wb_xics_ics_in.adr <= (others => '0');
+ wb_xics_ics_in.adr(11 downto 0) <= wb_sio_out.adr(11 downto 0);
+ wb_xics_ics_in.cyc <= '0';
wb_ext_io_in <= wb_sio_out;
wb_ext_io_in.cyc <= '0';
wb_ext_is_dram_csr <= '0';
wb_ext_is_dram_init <= '0';
+ wb_ext_is_eth <= '0';
-- Default response, ack & return all 1's
wb_sio_in.dat <= (others => '1');
elsif wb_sio_out.adr(23 downto 16) = x"00" and HAS_DRAM then
wb_ext_is_dram_csr <= '1';
ext_valid := true;
+ elsif wb_sio_out.adr(23 downto 16) = x"02" and HAS_LITEETH then
+ wb_ext_is_eth <= '1';
+ ext_valid := true;
+ elsif wb_sio_out.adr(23 downto 16) = x"03" and HAS_LITEETH then
+ wb_ext_is_eth <= '1';
+ ext_valid := true;
+ elsif wb_sio_out.adr(21 downto 14) = x"04" and HAS_LPC_SLAVE then
+ wb_ext_is_lpc_slave <= '1';
+ ext_valid := true;
+ elsif wb_sio_out.adr(21 downto 14) = x"05" and HAS_TERCEL then
+ wb_ext_is_tercel <= '1';
+ ext_valid := true;
end if;
if ext_valid then
wb_ext_io_in.cyc <= wb_sio_out.cyc;
when SLAVE_IO_UART =>
wb_uart0_in.cyc <= wb_sio_out.cyc;
wb_sio_in <= wb_uart0_out;
- when SLAVE_IO_ICP_0 =>
- wb_xics0_in.cyc <= wb_sio_out.cyc;
- wb_sio_in <= wb_xics0_out;
+ when SLAVE_IO_ICP =>
+ wb_xics_icp_in.cyc <= wb_sio_out.cyc;
+ wb_sio_in <= wb_xics_icp_out;
+ when SLAVE_IO_ICS =>
+ wb_xics_ics_in.cyc <= wb_sio_out.cyc;
+ wb_sio_in <= wb_xics_ics_out;
+ when SLAVE_IO_UART1 =>
+ wb_uart1_in.cyc <= wb_sio_out.cyc;
+ wb_sio_in <= wb_uart1_out;
when SLAVE_IO_SPI_FLASH_MAP =>
-- Clear top bits so they don't make their way to the
-- fash chip.
wb_spiflash_in.adr(29 downto 28) <= "00";
wb_spiflash_in.cyc <= wb_sio_out.cyc;
wb_sio_in <= wb_spiflash_out;
- wb_spiflash_is_map <= '1';
- when SLAVE_IO_SPI_FLASH_REG =>
- wb_spiflash_in.cyc <= wb_sio_out.cyc;
- wb_sio_in <= wb_spiflash_out;
- wb_spiflash_is_reg <= '1';
when others =>
end case;
DRAM_INIT_SIZE => DRAM_INIT_SIZE,
CLK_FREQ => CLK_FREQ,
HAS_SPI_FLASH => HAS_SPI_FLASH,
- SPI_FLASH_OFFSET => SPI_FLASH_OFFSET
+ SPI_FLASH_OFFSET => SPI_FLASH_OFFSET,
+ HAS_LITEETH => HAS_LITEETH,
+ UART0_IS_16550 => UART0_IS_16550,
+ HAS_UART1 => HAS_UART1
)
port map(
clk => system_clk,
soc_reset => open -- XXX TODO
);
- -- Simulated memory and UART
+ --
+ -- UART0
+ --
+ -- Either potato (legacy) or 16550
+ --
+ uart0_pp: if not UART0_IS_16550 generate
+ uart0: entity work.pp_soc_uart
+ generic map(
+ FIFO_DEPTH => 32
+ )
+ port map(
+ clk => system_clk,
+ reset => rst_uart,
+ txd => uart0_txd,
+ rxd => uart0_rxd,
+ irq => uart0_irq,
+ wb_adr_in => wb_uart0_in.adr(11 downto 0),
+ wb_dat_in => wb_uart0_in.dat(7 downto 0),
+ wb_dat_out => uart0_dat8,
+ wb_cyc_in => wb_uart0_in.cyc,
+ wb_stb_in => wb_uart0_in.stb,
+ wb_we_in => wb_uart0_in.we,
+ wb_ack_out => wb_uart0_out.ack
+ );
+ end generate;
- -- UART0 wishbone slave
- uart0: entity work.pp_soc_uart
- generic map(
- FIFO_DEPTH => 32
- )
- port map(
- clk => system_clk,
- reset => rst_uart,
- txd => uart0_txd,
- rxd => uart0_rxd,
- irq => int_level_in(0),
- wb_adr_in => wb_uart0_in.adr(11 downto 0),
- wb_dat_in => wb_uart0_in.dat(7 downto 0),
- wb_dat_out => uart_dat8,
- wb_cyc_in => wb_uart0_in.cyc,
- wb_stb_in => wb_uart0_in.stb,
- wb_we_in => wb_uart0_in.we,
- wb_ack_out => wb_uart0_out.ack
- );
- wb_uart0_out.dat <= x"000000" & uart_dat8;
+ uart0_16550 : if UART0_IS_16550 generate
+ signal irq_l : std_ulogic;
+ begin
+ uart0: uart_top
+ port map (
+ wb_clk_i => system_clk,
+ wb_rst_i => rst_uart,
+ wb_adr_i => wb_uart0_in.adr(4 downto 2),
+ wb_dat_i => wb_uart0_in.dat(7 downto 0),
+ wb_dat_o => uart0_dat8,
+ wb_we_i => wb_uart0_in.we,
+ wb_stb_i => wb_uart0_in.stb,
+ wb_cyc_i => wb_uart0_in.cyc,
+ wb_ack_o => wb_uart0_out.ack,
+ int_o => irq_l,
+ stx_pad_o => uart0_txd,
+ srx_pad_i => uart0_rxd,
+ rts_pad_o => open,
+ cts_pad_i => '1',
+ dtr_pad_o => open,
+ dsr_pad_i => '1',
+ ri_pad_i => '0',
+ dcd_pad_i => '1'
+ );
+
+ -- Add a register on the irq out, helps timing
+ uart0_irq_latch: process(system_clk)
+ begin
+ if rising_edge(system_clk) then
+ uart0_irq <= irq_l;
+ end if;
+ end process;
+ end generate;
+
+ wb_uart0_out.dat <= x"000000" & uart0_dat8;
wb_uart0_out.stall <= not wb_uart0_out.ack;
- spiflash_gen: if HAS_SPI_FLASH generate
- spiflash: entity work.spi_flash_ctrl
- generic map (
- DATA_LINES => SPI_FLASH_DLINES,
- DEF_CLK_DIV => SPI_FLASH_DEF_CKDV,
- DEF_QUAD_READ => SPI_FLASH_DEF_QUAD
- )
- port map(
- rst => rst_spi,
- clk => system_clk,
- wb_in => wb_spiflash_in,
- wb_out => wb_spiflash_out,
- wb_sel_reg => wb_spiflash_is_reg,
- wb_sel_map => wb_spiflash_is_map,
- sck => spi_flash_sck,
- cs_n => spi_flash_cs_n,
- sdat_o => spi_flash_sdat_o,
- sdat_oe => spi_flash_sdat_oe,
- sdat_i => spi_flash_sdat_i
- );
+ --
+ -- UART1
+ --
+ -- Always 16550 if it exists
+ --
+ uart1: if HAS_UART1 generate
+ signal irq_l : std_ulogic;
+ begin
+ uart1: uart_top
+ port map (
+ wb_clk_i => system_clk,
+ wb_rst_i => rst_uart,
+ wb_adr_i => wb_uart1_in.adr(4 downto 2),
+ wb_dat_i => wb_uart1_in.dat(7 downto 0),
+ wb_dat_o => uart1_dat8,
+ wb_we_i => wb_uart1_in.we,
+ wb_stb_i => wb_uart1_in.stb,
+ wb_cyc_i => wb_uart1_in.cyc,
+ wb_ack_o => wb_uart1_out.ack,
+ int_o => irq_l,
+ stx_pad_o => uart1_txd,
+ srx_pad_i => uart1_rxd,
+ rts_pad_o => open,
+ cts_pad_i => '1',
+ dtr_pad_o => open,
+ dsr_pad_i => '1',
+ ri_pad_i => '0',
+ dcd_pad_i => '1'
+ );
+ -- Add a register on the irq out, helps timing
+ uart0_irq_latch: process(system_clk)
+ begin
+ if rising_edge(system_clk) then
+ uart1_irq <= irq_l;
+ end if;
+ end process;
+ wb_uart1_out.dat <= x"000000" & uart1_dat8;
+ wb_uart1_out.stall <= not wb_uart1_out.ack;
end generate;
- no_spi0_gen: if not HAS_SPI_FLASH generate
- wb_spiflash_out.dat <= (others => '1');
- wb_spiflash_out.ack <= wb_spiflash_in.cyc and wb_spiflash_in.stb;
- wb_spiflash_out.stall <= wb_spiflash_in.cyc and not wb_spiflash_out.ack;
+ no_uart1 : if not HAS_UART1 generate
+ wb_uart1_out.dat <= x"00000000";
+ wb_uart1_out.ack <= wb_uart1_in.cyc and wb_uart1_in.stb;
+ wb_uart1_out.stall <= '0';
+ uart1_irq <= '0';
end generate;
- xics0: entity work.xics
+ xics_icp: entity work.xics_icp
+ port map(
+ clk => system_clk,
+ rst => rst_xics,
+ wb_in => wb_xics_icp_in,
+ wb_out => wb_xics_icp_out,
+ ics_in => ics_to_icp,
+ core_irq_out => core_ext_irq
+ );
+
+ xics_ics: entity work.xics_ics
generic map(
- LEVEL_NUM => 16
+ SRC_NUM => 16,
+ PRIO_BITS => 3
)
port map(
clk => system_clk,
rst => rst_xics,
- wb_in => wb_xics0_in,
- wb_out => wb_xics0_out,
+ wb_in => wb_xics_ics_in,
+ wb_out => wb_xics_ics_out,
int_level_in => int_level_in,
- core_irq_out => core_ext_irq
+ icp_out => ics_to_icp
);
+ -- Assign external interrupts
+ interrupts: process(all)
+ begin
+ int_level_in <= (others => '0');
+ int_level_in(0) <= uart0_irq;
+ int_level_in(1) <= ext_irq_eth;
+ int_level_in(2) <= uart1_irq;
+ end process;
+
-- BRAM Memory slave
bram: if MEMORY_SIZE /= 0 generate
bram0: entity work.wishbone_bram_wrapper
wb_in => wishbone_debug_in,
wb_out => wishbone_debug_out);
+--pragma synthesis_off
+ wb_x_state: process(system_clk)
+ begin
+ if rising_edge(system_clk) then
+ if not rst then
+ -- Wishbone arbiter
+ assert not(is_x(wb_masters_out(0).cyc)) and not(is_x(wb_masters_out(0).stb)) severity failure;
+ assert not(is_x(wb_masters_out(1).cyc)) and not(is_x(wb_masters_out(1).stb)) severity failure;
+ assert not(is_x(wb_masters_out(2).cyc)) and not(is_x(wb_masters_out(2).stb)) severity failure;
+ assert not(is_x(wb_masters_out(3).cyc)) and not(is_x(wb_masters_out(3).stb)) severity failure;
+ assert not(is_x(wb_masters_in(0).ack)) severity failure;
+ assert not(is_x(wb_masters_in(1).ack)) severity failure;
+ assert not(is_x(wb_masters_in(2).ack)) severity failure;
+ assert not(is_x(wb_masters_in(3).ack)) severity failure;
+
+ -- Main memory wishbones
+ assert not(is_x(wb_bram_in.cyc)) and not (is_x(wb_bram_in.stb)) severity failure;
+ assert not(is_x(wb_dram_in.cyc)) and not (is_x(wb_dram_in.stb)) severity failure;
+ assert not(is_x(wb_io_in.cyc)) and not (is_x(wb_io_in.stb)) severity failure;
+ assert not(is_x(wb_bram_out.ack)) severity failure;
+ assert not(is_x(wb_dram_out.ack)) severity failure;
+ assert not(is_x(wb_io_out.ack)) severity failure;
+
+ -- I/O wishbones
+ assert not(is_x(wb_uart0_in.cyc)) and not(is_x(wb_uart0_in.stb)) severity failure;
+ assert not(is_x(wb_uart1_in.cyc)) and not(is_x(wb_uart1_in.stb)) severity failure;
+ assert not(is_x(wb_spiflash_in.cyc)) and not(is_x(wb_spiflash_in.stb)) severity failure;
+ assert not(is_x(wb_xics_icp_in.cyc)) and not(is_x(wb_xics_icp_in.stb)) severity failure;
+ assert not(is_x(wb_xics_ics_in.cyc)) and not(is_x(wb_xics_ics_in.stb)) severity failure;
+ assert not(is_x(wb_ext_io_in.cyc)) and not(is_x(wb_ext_io_in.stb)) severity failure;
+ assert not(is_x(wb_syscon_in.cyc)) and not(is_x(wb_syscon_in.stb)) severity failure;
+ assert not(is_x(wb_uart0_out.ack)) severity failure;
+ assert not(is_x(wb_uart1_out.ack)) severity failure;
+ assert not(is_x(wb_spiflash_out.ack)) severity failure;
+ assert not(is_x(wb_xics_icp_out.ack)) severity failure;
+ assert not(is_x(wb_xics_ics_out.ack)) severity failure;
+ assert not(is_x(wb_ext_io_out.ack)) severity failure;
+ assert not(is_x(wb_syscon_out.ack)) severity failure;
+ end if;
+ end if;
+ end process;
+--pragma synthesis_on
+
+ -- LPC slave DMA
+ wb_lpc_slave_in <= wishbone_lpc_in;
+ wishbone_lpc_out <= wb_lpc_slave_out;
end architecture behaviour;
projects / microwatt.git / blobdiff