Add Tercel PHY reset synchronization

[microwatt.git] / spi_rxtx.vhdl

diff --git a/spi_rxtx.vhdl b/spi_rxtx.vhdl
index 13acdf367b3e2a4981502b88f12ecd26e152187d..b2de245413108ea9711586a9d4c5fd697ea68051 100644 (file)
--- a/spi_rxtx.vhdl
+++ b/spi_rxtx.vhdl
@@ -258,12 +258,16 @@ begin
     count_bit: process(clk)
     begin
         if rising_edge(clk) then
-            if start_cmd = '1' then
-                bit_count <= cmd_clks_i;
-            elsif state /= DATA then
-                bit_count <= (others => '1');
-            elsif sck_recv = '1' then
-                bit_count <= std_ulogic_vector(unsigned(bit_count) - 1);
+            if rst = '1' then
+                bit_count <= (others => '0');
+            else
+                if start_cmd = '1' then
+                    bit_count <= cmd_clks_i;
+                elsif state /= DATA then
+                    bit_count <= (others => '1');
+                elsif sck_recv = '1' then
+                    bit_count <= std_ulogic_vector(unsigned(bit_count) - 1);
+                end if;
             end if;
         end if;
     end process;