working on adding signed multiplication -- needed for toom-cook

[bigint-presentation-code.git] / src / bigint_presentation_code / compiler_ir.py

diff --git a/src/bigint_presentation_code/compiler_ir.py b/src/bigint_presentation_code/compiler_ir.py
index 756615df8e4ce02a4fcff7125c7fa5318e7005c3..ba5ada9b17bf341e7ec5431e5c0d58d364669e84 100644 (file)
--- a/src/bigint_presentation_code/compiler_ir.py
+++ b/src/bigint_presentation_code/compiler_ir.py
@@ -16,6 +16,12 @@ from bigint_presentation_code.util import (BitSet, FBitSet, FMap, InternedMeta,
                                            OFSet, OSet)
 
 
+GPR_SIZE_IN_BYTES = 8
+BITS_IN_BYTE = 8
+GPR_SIZE_IN_BITS = GPR_SIZE_IN_BYTES * BITS_IN_BYTE
+GPR_VALUE_MASK = (1 << GPR_SIZE_IN_BITS) - 1
+
+
 @final
 class Fn:
     def __init__(self):
@@ -1221,6 +1227,36 @@ class OpKind(Enum):
     _SIM_FNS[SvMAddEDU] = lambda: OpKind.__svmaddedu_sim
     _GEN_ASMS[SvMAddEDU] = lambda: OpKind.__svmaddedu_gen_asm
 
+    @staticmethod
+    def __sradi_sim(op, state):
+        # type: (Op, BaseSimState) -> None
+        rs, = state[op.input_vals[0]]
+        imm = op.immediates[0]
+        if rs >= 1 << (GPR_SIZE_IN_BITS - 1):
+            rs -= 1 << GPR_SIZE_IN_BITS
+        v = rs >> imm
+        RA = v & GPR_VALUE_MASK
+        CA = (RA << imm) != rs
+        state[op.outputs[0]] = RA,
+        state[op.outputs[1]] = CA,
+
+    @staticmethod
+    def __sradi_gen_asm(op, state):
+        # type: (Op, GenAsmState) -> None
+        RA = state.sgpr(op.outputs[0])
+        RS = state.sgpr(op.input_vals[1])
+        imm = op.immediates[0]
+        state.writeln(f"sradi {RA}, {RS}, {imm}")
+    SRADI = GenericOpProperties(
+        demo_asm="sradi RA, RS, imm",
+        inputs=[OD_BASE_SGPR],
+        outputs=[OD_BASE_SGPR.with_write_stage(OpStage.Late),
+                 OD_CA.with_write_stage(OpStage.Late)],
+        immediates=[range(GPR_SIZE_IN_BITS)],
+    )
+    _SIM_FNS[SRADI] = lambda: OpKind.__sradi_sim
+    _GEN_ASMS[SRADI] = lambda: OpKind.__sradi_gen_asm
+
     @staticmethod
     def __setvli_sim(op, state):
         # type: (Op, BaseSimState) -> None
@@ -1971,12 +2007,6 @@ class Op:
         self.kind.gen_asm(self, state)
 
 
-GPR_SIZE_IN_BYTES = 8
-BITS_IN_BYTE = 8
-GPR_SIZE_IN_BITS = GPR_SIZE_IN_BYTES * BITS_IN_BYTE
-GPR_VALUE_MASK = (1 << GPR_SIZE_IN_BITS) - 1
-
-
 @plain_data(frozen=True, repr=False)
 class BaseSimState(metaclass=ABCMeta):
     __slots__ = "memory",