add emmc dummy peripheral

[pinmux.git] / src / bsv / Makefile.template

diff --git a/src/bsv/Makefile.template b/src/bsv/Makefile.template
index bd81d522df636e789a67f01cd337cb0c76ff478f..ab58b51fdd626215f17dac3df727907bd22a16ac 100644 (file)
--- a/src/bsv/Makefile.template
+++ b/src/bsv/Makefile.template
@@ -1,12 +1,13 @@
 ### Makefile for the cclass project
 
 TOP_MODULE:=mkSoc
-TOP_FILE:=soc.bsv
+TOP_FILE:=socgen.bsv
 TOP_DIR:=./
 WORKING_DIR := $(shell pwd)
 
 BSVINCDIR:= .:%/Prelude:%/Libraries:%/Libraries/BlueNoC:./bsv_lib/
 BSVINCDIR:= $(BSVINCDIR):../../../src/core/src/core
+BSVINCDIR:= $(BSVINCDIR):../../../src/core/src/core/fpu
 BSVINCDIR:= $(BSVINCDIR):../../../src/core/src/lib
 BSVINCDIR:= $(BSVINCDIR):../../../src/peripherals/src/core
 BSVINCDIR:= $(BSVINCDIR):../../../src/peripherals/src/uncore/axi4
@@ -18,10 +19,13 @@ BSVINCDIR:= $(BSVINCDIR):../../../src/peripherals/src/peripherals/rgbttl
 BSVINCDIR:= $(BSVINCDIR):../../../src/peripherals/src/peripherals/i2c
 BSVINCDIR:= $(BSVINCDIR):../../../src/peripherals/src/peripherals/mux
 BSVINCDIR:= $(BSVINCDIR):../../../src/peripherals/src/peripherals/plic
+BSVINCDIR:= $(BSVINCDIR):../../../src/peripherals/src/peripherals/clint
+BSVINCDIR:= $(BSVINCDIR):../../../src/peripherals/src/peripherals/sdram
 BSVINCDIR:= $(BSVINCDIR):../../../src/peripherals/src/peripherals/pwm
 BSVINCDIR:= $(BSVINCDIR):../../../src/peripherals/src/peripherals/qspi
 BSVINCDIR:= $(BSVINCDIR):../../../src/peripherals/src/peripherals/spi
 BSVINCDIR:= $(BSVINCDIR):../../../src/peripherals/src/peripherals/sdmmc
+BSVINCDIR:= $(BSVINCDIR):../../../src/peripherals/src/peripherals/emmc
 BSVINCDIR:= $(BSVINCDIR):../../../src/peripherals/src/peripherals/flexbus
 BSVINCDIR:= $(BSVINCDIR):../../../src/peripherals/src/peripherals/jtagdtm
 BSVINCDIR:= $(BSVINCDIR):../../../src/peripherals/src/peripherals/uart
@@ -49,7 +53,18 @@ gen_verilog: check-restore check-blue
        @echo Compiling mkTbSoc in Verilog for simulations ...
        @mkdir -p $(BSVBUILDDIR); 
        @mkdir -p $(VERILOGDIR); 
-       bsc -u -verilog -elab -vdir $(VERILOGDIR) -bdir $(BSVBUILDDIR) -info-dir $(BSVBUILDDIR) $(define_macros) -D verilog=True $(BSVCOMPILEOPTS) -verilog-filter ${BLUESPECDIR}/bin/basicinout -p $(BSVINCDIR) -g $(TOP_MODULE) $(TOP_DIR)/$(TOP_FILE) 2>&1 | tee bsv_compile.log
+       bsc -u -verilog -elab -vdir $(VERILOGDIR) -bdir $(BSVBUILDDIR) \
+               -info-dir $(BSVBUILDDIR) $(define_macros) \
+               -D RV64=True -D muldiv=True -D sequential=True \
+               -D atomic=True -D spfpu=True -D dpfpu=True \
+               -D bpu=True -D MMU=True -D perf=True \
+               -D prefetch=True -D CLINT=True \
+               -D      simulate=True -D SDRAM=True \
+               -D GPIO_MUX=True \
+               -D verilog=True $(BSVCOMPILEOPTS) -verilog-filter \
+               ${BLUESPECDIR}/bin/basicinout -p $(BSVINCDIR) \
+               -g $(TOP_MODULE) $(TOP_DIR)/$(TOP_FILE) \
+               2>&1 | tee bsv_compile.log
        @echo Compilation finished
 
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