vectorise pincon sync

[pinmux.git] / src / bsv / peripheral_gen / base.py

diff --git a/src/bsv/peripheral_gen/base.py b/src/bsv/peripheral_gen/base.py
index 7b8ca982095b0ba526c929c007f9d51521df5ff9..fd3038478791830c4ca2556f25ee5f75dddb6dd3 100644 (file)
--- a/src/bsv/peripheral_gen/base.py
+++ b/src/bsv/peripheral_gen/base.py
@@ -196,6 +196,20 @@ else"""
                     ret += cn
         return '\n'.join(ret)
 
+    def _mk_vpincon(self, name, count, ptyp, typ, pname):
+        ret = []
+        if ptyp == 'fast':
+            sname = self.get_iname(count)
+            ps = "slow_peripherals.%s" % sname
+        else:
+            sname = self.peripheral.iname().format(count)
+            ps = "pinmux.peripheral_side.%s" % sname
+        n = self.get_iname(count)
+        ps_ = "{0}.{1}".format(ps, pname)
+        ret += self._mk_actual_connection(typ, name, count, typ,
+                                          pname, ps_, n, pname)
+        return '\n'.join(ret)
+
     def _mk_actual_connection(self, ctype, name, count, typ,
                               pname, ps, n, fname):
         ret = []
@@ -227,6 +241,7 @@ else"""
                             sync, n))
         return ret
 
+
     def _mk_clk_con(self, name, count, ctype):
         ret = []
         ck = self.get_clock_reset(name, count)
@@ -265,6 +280,23 @@ Ifc_sync#({0}) {1}_sync <-mksyncconnection(
                 ret.append(template.format("Bit#(1)", n_, spc, ck))
         return '\n'.join(ret)
 
+    def _mk_clk_vcon(self, name, count, ctype, typ, pname, bitspec):
+        ck = self.get_clock_reset(name, count)
+        if ck == PBase.get_clock_reset(self, name, count):
+            return ''
+        if ctype == 'slow':
+            spc = "sp_clock, sp_reset"
+        else:
+            spc = ck
+            ck = "core_clock, core_reset"
+        template = """\
+Ifc_sync#({0}) {1}_sync <-mksyncconnection(
+            {2}, {3});"""
+
+        n_ = "{0}{1}".format(name, count)
+        n_ = '{0}_{1}'.format(n_, pname)
+        return template.format(bitspec,  n_, ck, spc)
+
 
     def mk_cellconn(self, *args):
         return ''