add rst0 to sdram

[pinmux.git] / src / bsv / peripheral_gen / sdram.py

diff --git a/src/bsv/peripheral_gen/sdram.py b/src/bsv/peripheral_gen/sdram.py
index 1158ebf5ba989d31ca253cee56a093fb3f1bdda3..afc6908ede4b9fbac49f40397ade261c274511f4 100644 (file)
--- a/src/bsv/peripheral_gen/sdram.py
+++ b/src/bsv/peripheral_gen/sdram.py
@@ -18,11 +18,14 @@ class sdram(PBase):
         return "// (*always_ready*) interface " + \
                 "Ifc_sdram_out sdr{0}_out;".format(count)
 
+    def get_clk_spc(self, typ):
+        return "clk0, rst0"
+
     def get_clock_reset(self, name, count):
         return "slow_clock, slow_reset"
 
     def mkfast_peripheral(self):
-        return "Ifc_sdr_slave sdr{0} <- mksdr_axi4_slave(clk0);"
+        return "Ifc_sdr_slave sdr{0} <- mksdr_axi4_slave(clk0, rst0);"
 
     def _mk_connection(self, name=None, count=0):
         return ["sdr{0}.axi4_slave_sdram",
@@ -32,6 +35,7 @@ class sdram(PBase):
         return {'sdrwen': 'ifc_sdram_out.osdr_we_n',
                 'sdrcsn0': 'ifc_sdram_out.osdr_cs_n',
                 'sdrcke': 'ifc_sdram_out.osdr_cke',
+                'sdrclk': 'ifc_sdram_out.osdr_clock',
                 'sdrrasn': 'ifc_sdram_out.osdr_ras_n',
                 'sdrcasn': 'ifc_sdram_out.osdr_cas_n',
                 }.get(pname, '')