bname = self.axibase(name, ifacenum)
bend = self.axiend(name, ifacenum)
comment = "%d 32-bit regs" % self.num_axi_regs32()
- return (" `define%(bname)s 'h%(start)08X\n"
- " `define%(bend)s 'h%(end)08X // %(comment)s" % locals(),
+ return (" `define %(bname)s 'h%(start)08X\n"
+ " `define %(bend)s 'h%(end)08X // %(comment)s" % locals(),
offs)
def axi_slave_name(self, name, ifacenum):
else""".format(bname, bend, name)
def mk_pincon(self, name, count):
+ # TODO: really should be using bsv.interface_decl.Interfaces
+ # pin-naming rules.... logic here is hard-coded to duplicate
+ # it (see Interface.__init__ outen)
ret = []
for p in self.peripheral.pinspecs:
typ = p['type']
pname = p['name']
#n = "{0}{1}".format(self.name, self.mksuffix(name, count))
- n = name#"{0}{1}".format(self.name, self.mksuffix(name, count))
+ n = name # "{0}{1}".format(self.name, self.mksuffix(name, count))
ret.append(" //%s %s" % (n, str(p)))
sname = self.peripheral.pname(pname).format(count)
ps = "pinmux.peripheral_side.%s" % sname
if typ == 'out' or typ == 'inout':
- ret.append(" rule con_%s%d_%s_out" % (name, count, pname))
+ ret.append(" rule con_%s%d_%s_out;" % (name, count, pname))
fname = self.pinname_out(pname)
if fname:
- ret.append(" {0}_out({1}.{2});".format(ps, n, fname))
+ if p.get('outen'):
+ ps_ = ps + '_out'
+ else:
+ ps_ = ps
+ n_ = "{0}{1}".format(n, count)
+ ret.append(" {0}({1}.{2});".format(ps_, n_, fname))
fname = None
if p.get('outen'):
fname = self.pinname_outen(pname)
if fname:
- fname = "{0}{1}.{2}".format(n, count, fname)
+ if isinstance(fname, str):
+ fname = "{0}{1}.{2}".format(n, count, fname)
fname = self.pinname_tweak(pname, 'outen', fname)
ret.append(" {0}_outen({1});".format(ps, fname))
ret.append(" endrule")
if typ == 'in' or typ == 'inout':
fname = self.pinname_in(pname)
if fname:
- ret.append(" rule con_%s%d_%s_in" % (name, count, pname))
- ret.append(" {1}.{2}({0}_in);".format(ps, n, fname))
+ if p.get('outen'):
+ ps_ = ps + '_in'
+ else:
+ ps_ = ps
+ ret.append(
+ " rule con_%s%d_%s_in;" %
+ (name, count, pname))
+ ret.append(" {1}.{2}({0});".format(ps_, n, fname))
ret.append(" endrule")
return '\n'.join(ret)
def mk_cellconn(self, *args):
return ''
- def mkslow_peripheral(self):
+ def mkslow_peripheral(self, size=0):
return ''
def mksuffix(self, name, i):
return i
def __mk_connection(self, con, aname):
- txt = " mkConnection (slow_fabric.v_to_slaves\n" + \
- " [fromInteger(valueOf({1}))],\n" + \
- " {0});"
+ txt = " mkConnection (slow_fabric.v_to_slaves\n" + \
+ " [fromInteger(valueOf({1}))],\n" + \
+ " {0});"
print "PBase __mk_connection", self.name, aname
if not con:
def pinname_tweak(self, pname, typ, txt):
return txt
+
class uart(PBase):
def slowimport(self):
def num_axi_regs32(self):
return 8
- def mkslow_peripheral(self):
+ def mkslow_peripheral(self, size=0):
return " Uart16550_AXI4_Lite_Ifc uart{0} <- \n" + \
" mkUart16550(clocked_by uart_clock,\n" + \
" reset_by uart_reset, sp_clock, sp_reset);"
def num_axi_regs32(self):
return 2
- def mkslow_peripheral(self):
+ def mkslow_peripheral(self, size=0):
return " //Ifc_Uart_bs uart{0} <-" + \
" // mkUart_bs(clocked_by uart_clock,\n" + \
" // reset_by uart_reset,sp_clock, sp_reset);" +\
def num_axi_regs32(self):
return 8
- def mkslow_peripheral(self):
+ def mkslow_peripheral(self, size=0):
return " I2C_IFC twi{0} <- mkI2CController();"
def _mk_connection(self, name=None, count=0):
def num_axi_regs32(self):
return 13
- def mkslow_peripheral(self):
+ def mkslow_peripheral(self, size=0):
return " Ifc_qspi qspi{0} <- mkqspi();"
def _mk_connection(self, name=None, count=0):
return "qspi{0}.slave"
+ def pinname_out(self, pname):
+ return {'ck': 'out.clk_o',
+ 'nss': 'out.ncs_o',
+ 'io0': 'out.io_o[0]',
+ 'io1': 'out.io_o[1]',
+ 'io2': 'out.io_o[2]',
+ 'io3': 'out.io_o[3]',
+ }.get(pname, '')
+
+ def pinname_outen(self, pname):
+ return {'ck': 1,
+ 'nss': 1,
+ 'io0': 'out.io_enable[0]',
+ 'io1': 'out.io_enable[1]',
+ 'io2': 'out.io_enable[2]',
+ 'io3': 'out.io_enable[3]',
+ }.get(pname, '')
+
+ def mk_pincon(self, name, count):
+ ret = [PBase.mk_pincon(self, name, count)]
+ # special-case for gpio in, store in a temporary vector
+ plen = len(self.peripheral.pinspecs)
+ ret.append(" // XXX NSS and CLK are hard-coded master")
+ ret.append(" // TODO: must add qspi slave-mode")
+ ret.append(" // all ins done in one rule from 4-bitfield")
+ ret.append(" rule con_%s%d_io_in;" % (name, count))
+ ret.append(" {0}{1}.out.io_i({{".format(name, count))
+ for i, p in enumerate(self.peripheral.pinspecs):
+ typ = p['type']
+ pname = p['name']
+ if not pname.startswith('io'):
+ continue
+ idx = pname[1:]
+ n = name
+ sname = self.peripheral.pname(pname).format(count)
+ ps = "pinmux.peripheral_side.%s_in" % sname
+ comma = '' if i == 5 else ','
+ ret.append(" {0}{1}".format(ps, comma))
+ ret.append(" });")
+ ret.append(" endrule")
+ return '\n'.join(ret)
+
class pwm(PBase):
def num_axi_regs32(self):
return 4
- def mkslow_peripheral(self):
+ def mkslow_peripheral(self, size=0):
return " Ifc_PWM_bus pwm{0}_bus <- mkPWM_bus(sp_clock);"
def _mk_connection(self, name=None, count=0):
return "pwm{0}_bus.axi4_slave"
+ def pinname_out(self, pname):
+ return {'out': 'pwm_io.pwm_o'}.get(pname, '')
+
class gpio(PBase):
(ret2, x) = PBase.axi_slave_idx(self, idx, "mux", ifacenum)
return ("%s\n%s" % (ret, ret2), 2)
- def mkslow_peripheral(self):
- return " MUX#(%(name)s) mux{0} <- mkmux();\n" + \
- " GPIO#(%(name)s) gpio{0} <- mkgpio();" % \
- {'name': self.name}
+ def mkslow_peripheral(self, size=0):
+ print "gpioslow", self.peripheral, dir(self.peripheral)
+ size = len(self.peripheral.pinspecs)
+ return " MUX#(%d) mux{0} <- mkmux();\n" % size + \
+ " GPIO#(%d) gpio{0} <- mkgpio();" % size
def mk_connection(self, count):
print "GPIO mk_conn", self.name, count
ret = [PBase.mk_pincon(self, name, count)]
# special-case for gpio in, store in a temporary vector
plen = len(self.peripheral.pinspecs)
- ret.append(" rule con_%s%d_in" % (name, count))
+ ret.append(" rule con_%s%d_in;" % (name, count))
ret.append(" Vector#({0},Bit#(1)) temp;".format(plen))
for p in self.peripheral.pinspecs:
typ = p['type']
#print ("ifc", name, rdef, offs)
ret.append(rdef)
start += offs
- ret.append("typedef %d LastGen_slave_num" % (start - 1))
+ ret.append("typedef %d LastGen_slave_num;" % (start - 1))
decls = '\n'.join(list(filter(None, ret)))
return axi_slave_declarations.format(decls)
ret.append(txt)
return '\n'.join(list(filter(None, ret)))
+
class PFactory(object):
def getcls(self, name):
for k, v in {'uart': uart,
- 'rs232': rs232,
- 'twi': twi,
- 'qspi': qspi,
- 'pwm': pwm,
- 'gpio': gpio
- }.items():
+ 'rs232': rs232,
+ 'twi': twi,
+ 'qspi': qspi,
+ 'pwm': pwm,
+ 'gpio': gpio
+ }.items():
if name.startswith(k):
return v
return None
projects / pinmux.git / blobdiff