add in quart
[pinmux.git] / src / bsv / peripheral_gen.py
index 0af60d003de3d67c4abad255932ca32d75d02e13..5326144bcae74927cbc0ae2fb704eafcdf5d5e38 100644 (file)
@@ -9,6 +9,15 @@ class PBase(object):
     def slowifdeclmux(self):
         return ''
 
+    def slowifinstance(self):
+        return ''
+
+    def slowimport(self):
+        return ''
+
+    def num_axi_regs32(self):
+        return 0
+
     def slowifdecl(self):
         return ''
 
@@ -23,6 +32,8 @@ class PBase(object):
     def axi_reg_def(self, start, name, ifacenum):
         name = name.upper()
         offs = self.num_axi_regs32() * 4 * 16
+        if offs == 0:
+            return ('', 0)
         end = start + offs - 1
         bname = self.axibase(name, ifacenum)
         bend = self.axiend(name, ifacenum)
@@ -64,10 +75,10 @@ class PBase(object):
             if typ == 'out' or typ == 'inout':
                 ret.append("    rule con_%s%d_%s_out;" % (name, count, pname))
                 fname = self.pinname_out(pname)
-                if not n.startswith('gpio'): # XXX EURGH! horrible hack
-                  n_ = "{0}{1}".format(n, count)
+                if not n.startswith('gpio'):  # XXX EURGH! horrible hack
+                    n_ = "{0}{1}".format(n, count)
                 else:
-                  n_ = n
+                    n_ = n
                 if fname:
                     if p.get('outen'):
                         ps_ = ps + '_out'
@@ -94,7 +105,9 @@ class PBase(object):
                         "    rule con_%s%d_%s_in;" %
                         (name, count, pname))
                     n_ = "{0}{1}".format(n, count)
-                    ret.append("      {1}.{2}({0});".format(ps_, n_, fname))
+                    n_ = '{0}.{1}'.format(n_, fname)
+                    n_ = self.ifname_tweak(pname, 'in', n_)
+                    ret.append("      {1}({0});".format(ps_, n_))
                     ret.append("    endrule")
         return '\n'.join(ret)
 
@@ -139,6 +152,9 @@ class PBase(object):
     def pinname_outen(self, pname):
         return ''
 
+    def ifname_tweak(self, pname, typ, txt):
+        return txt
+
     def pinname_tweak(self, pname, typ, txt):
         return txt
 
@@ -171,31 +187,51 @@ class uart(PBase):
         return {'rx': 'coe_rs232.sin'}.get(pname, '')
 
 
-class qquart(PBase):
+class quart(PBase):
 
     def slowimport(self):
         return "          import Uart16550         :: *;"
 
     def slowifdecl(self):
-        return "            interface RS232_PHY_Ifc uart{0}_coe;\n" + \
-               "            method Bit#(1) uart{0}_intr;"
+        return "            interface RS232_PHY_Ifc quart{0}_coe;\n" + \
+               "            method Bit#(1) quart{0}_intr;"
 
     def num_axi_regs32(self):
         return 8
 
     def mkslow_peripheral(self, size=0):
-        return "        Uart16550_AXI4_Lite_Ifc uart{0} <- \n" + \
+        return "        Uart16550_AXI4_Lite_Ifc quart{0} <- \n" + \
                "                mkUart16550(clocked_by sp_clock,\n" + \
                "                    reset_by uart_reset, sp_clock, sp_reset);"
 
     def _mk_connection(self, name=None, count=0):
-        return "uart{0}.slave_axi_uart"
+        return "quart{0}.slave_axi_uart"
 
     def pinname_out(self, pname):
-        return {'tx': 'coe_rs232.sout'}.get(pname, '')
+        return {'tx' : 'coe_rs232.modem_output_stx',
+                'rts': 'coe_rs232.modem_output_rts',
+               }.get(pname, '')
 
-    def pinname_in(self, pname):
-        return {'rx': 'coe_rs232.sin'}.get(pname, '')
+    def _pinname_in(self, pname):
+        return {'rx': 'coe_rs232.modem_input.srx', 
+                'cts': 'coe_rs232.modem_input.cts'
+               }.get(pname, '')
+
+    def mk_pincon(self, name, count):
+        ret = [PBase.mk_pincon(self, name, count)]
+        size = len(self.peripheral.pinspecs)
+        ret.append(eint_pincon_template.format(size))
+        ret.append("    rule con_%s%d_io_in;" % (name, count))
+        ret.append("       {0}{1}.coe_rs232.modem_input(".format(name, count))
+        for idx, pname in enumerate(['rx', 'cts']):
+            sname = self.peripheral.pname(pname).format(count)
+            ps = "pinmux.peripheral_side.%s" % sname
+            ret.append("            {0},".format(ps))
+        ret.append("            1'b1,1'b0,1'b1")
+        ret.append("        );")
+        ret.append("    endrule")
+
+        return '\n'.join(ret)
 
 
 class rs232(PBase):
@@ -264,6 +300,124 @@ class twi(PBase):
         return txt
 
 
+class eint(PBase):
+
+    def slowimport(self):
+        size = len(self.peripheral.pinspecs)
+        return "    `define NUM_EINTS %d" % size
+
+    def mkslow_peripheral(self, size=0):
+        size = len(self.peripheral.pinspecs)
+        return "        Wire#(Bit#(%d)) wr_interrupt <- mkWire();" % size
+
+    def axi_slave_name(self, name, ifacenum):
+        return ''
+
+    def axi_slave_idx(self, idx, name, ifacenum):
+        return ('', 0)
+
+    def axi_addr_map(self, name, ifacenum):
+        return ''
+
+    def ifname_tweak(self, pname, typ, txt):
+        if typ != 'in':
+            return txt
+        print "ifnameweak", pname, typ, txt
+        return "wr_interrupt[{0}] <= ".format(pname)
+
+    def mk_pincon(self, name, count):
+        ret = [PBase.mk_pincon(self, name, count)]
+        size = len(self.peripheral.pinspecs)
+        ret.append(eint_pincon_template.format(size))
+        ret.append("    rule con_%s%d_io_in;" % (name, count))
+        ret.append("    wr_interrupt <= ({")
+        for idx, p in enumerate(self.peripheral.pinspecs):
+            pname = p['name']
+            sname = self.peripheral.pname(pname).format(count)
+            ps = "pinmux.peripheral_side.%s" % sname
+            comma = '' if idx == size - 1 else ','
+            ret.append("             {0}{1}".format(ps, comma))
+        ret.append("        });")
+        ret.append("    endrule")
+
+        return '\n'.join(ret)
+
+
+eint_pincon_template = '''\
+    // TODO: offset i by the number of eints already used
+    for(Integer i=0;i<{0};i=i+ 1)begin
+      rule connect_int_to_plic(wr_interrupt[i]==1);
+                ff_gateway_queue[i].enq(1);
+                plic.ifc_external_irq[i].irq_frm_gateway(True);
+      endrule
+    end
+'''
+
+
+class jtag(PBase):
+
+    def axi_slave_name(self, name, ifacenum):
+        return ''
+
+    def axi_slave_idx(self, idx, name, ifacenum):
+        return ('', 0)
+
+    def axi_addr_map(self, name, ifacenum):
+        return ''
+
+    def slowifdeclmux(self):
+        return "            method  Action jtag_ms (Bit#(1) in);\n" +  \
+               "            method  Bit#(1) jtag_di;\n" + \
+               "            method  Action jtag_do (Bit#(1) in);\n" + \
+               "            method  Action jtag_ck (Bit#(1) in);"
+
+    def slowifinstance(self):
+        return jtag_method_template # bit of a lazy hack this...
+
+jtag_method_template = """\
+    method  Action jtag_ms (Bit#(1) in);
+      pinmux.peripheral_side.jtag_ms(in);
+    endmethod
+    method  Bit#(1) jtag_di=pinmux.peripheral_side.jtag_di;
+    method  Action jtag_do (Bit#(1) in);
+      pinmux.peripheral_side.jtag_do(in);
+    endmethod
+    method  Action jtag_ck (Bit#(1) in);
+      pinmux.peripheral_side.jtag_ck(in);
+    endmethod
+"""
+
+class sdmmc(PBase):
+
+    def slowimport(self):
+        return "        import sdcard_dummy              :: *;"
+
+    def slowifdecl(self):
+        return "            interface QSPI_out sd{0}_out;\n" + \
+               "            method Bit#(1) sd{0}_isint;"
+
+    def num_axi_regs32(self):
+        return 13
+
+    def mkslow_peripheral(self):
+        return "        Ifc_sdcard_dummy sd{0} <-  mksdcard_dummy();"
+
+    def _mk_connection(self, name=None, count=0):
+        return "sd{0}.slave"
+
+    def pinname_in(self, pname):
+        return "%s_in" % pname
+
+    def pinname_out(self, pname):
+        if pname.startswith('d'):
+            return "%s_out" % pname
+        return pname
+
+    def pinname_outen(self, pname):
+        if pname.startswith('d'):
+            return "%s_outen" % pname
+
+
 class spi(PBase):
 
     def slowimport(self):
@@ -280,7 +434,7 @@ class spi(PBase):
         return "        Ifc_qspi spi{0} <-  mkqspi();"
 
     def _mk_connection(self, name=None, count=0):
-        return "qspi{0}.slave"
+        return "spi{0}.slave"
 
     def pinname_out(self, pname):
         return {'clk': 'out.clk_o',
@@ -290,7 +444,7 @@ class spi(PBase):
                 }.get(pname, '')
 
     def pinname_outen(self, pname):
-        return {'ck': 1,
+        return {'clk': 1,
                 'nss': 1,
                 'mosi': 'out.io_enable[0]',
                 'miso': 'out.io_enable[1]',
@@ -301,7 +455,7 @@ class spi(PBase):
         # special-case for gpio in, store in a temporary vector
         plen = len(self.peripheral.pinspecs)
         ret.append("    // XXX NSS and CLK are hard-coded master")
-        ret.append("    // TODO: must add qspi slave-mode")
+        ret.append("    // TODO: must add spi slave-mode")
         ret.append("    // all ins done in one rule from 4-bitfield")
         ret.append("    rule con_%s%d_io_in;" % (name, count))
         ret.append("       {0}{1}.out.io_i({{".format(name, count))
@@ -309,7 +463,7 @@ class spi(PBase):
             sname = self.peripheral.pname(pname).format(count)
             ps = "pinmux.peripheral_side.%s_in" % sname
             ret.append("            {0},".format(ps))
-        ret.append("            0,0")
+        ret.append("            1'b0,1'b0")
         ret.append("        });")
         ret.append("    endrule")
         return '\n'.join(ret)
@@ -418,13 +572,13 @@ class gpio(PBase):
         name = name.upper()
         mname = 'mux' + name[4:]
         mname = mname.upper()
-        print "AXIslavenum", name,  mname
+        print "AXIslavenum", name, mname
         (ret, x) = PBase.axi_slave_idx(self, idx, name, ifacenum)
-        (ret2, x) = PBase.axi_slave_idx(self, idx+1, mname, ifacenum)
+        (ret2, x) = PBase.axi_slave_idx(self, idx + 1, mname, ifacenum)
         return ("%s\n%s" % (ret, ret2), 2)
 
     def mkslow_peripheral(self, size=0):
-        print "gpioslow", self.peripheral,  dir(self.peripheral)
+        print "gpioslow", self.peripheral, dir(self.peripheral)
         size = len(self.peripheral.pinspecs)
         return "        MUX#(%d) mux{0} <- mkmux();\n" % size + \
                "        GPIO#(%d) gpio{0} <- mkgpio();" % size
@@ -522,7 +676,8 @@ class PeripheralIface(object):
         if slow:
             self.slow = slow(ifacename)
             self.slow.peripheral = self
-        for fname in ['slowimport', 'slowifdecl', 'slowifdeclmux', 
+        for fname in ['slowimport', 
+                      'slowifinstance', 'slowifdecl', 'slowifdeclmux',
                       'mkslow_peripheral',
                       'mk_connection', 'mk_cellconn', 'mk_pincon']:
             fn = CallFn(self, fname)
@@ -563,6 +718,13 @@ class PeripheralInterfaces(object):
             ret.append(self.data[name].slowimport())
         return '\n'.join(list(filter(None, ret)))
 
+    def slowifinstance(self, *args):
+        ret = []
+        for (name, count) in self.ifacecount:
+            #print "slowimport", name, self.data[name].slowimport
+            ret.append(self.data[name].slowifinstance())
+        return '\n'.join(list(filter(None, ret)))
+
     def slowifdeclmux(self, *args):
         ret = []
         for (name, count) in self.ifacecount:
@@ -659,9 +821,13 @@ class PFactory(object):
         for k, v in {'uart': uart,
                      'rs232': rs232,
                      'twi': twi,
+                     'quart': quart,
                      'qspi': qspi,
                      'spi': spi,
                      'pwm': pwm,
+                     'eint': eint,
+                     'sd': sdmmc,
+                     'jtag': jtag,
                      'gpio': gpio
                      }.items():
             if name.startswith(k):