def __init__(self, name):
self.name = name
+ def slowifdeclmux(self):
+ return ''
+
+ def slowifinstance(self):
+ return ''
+
+ def slowimport(self):
+ return ''
+
+ def num_axi_regs32(self):
+ return 0
+
+ def slowifdecl(self):
+ return ''
+
def axibase(self, name, ifacenum):
name = name.upper()
return "%(name)s%(ifacenum)dBase" % locals()
def axi_reg_def(self, start, name, ifacenum):
name = name.upper()
offs = self.num_axi_regs32() * 4 * 16
+ if offs == 0:
+ return ('', 0)
end = start + offs - 1
bname = self.axibase(name, ifacenum)
bend = self.axiend(name, ifacenum)
comment = "%d 32-bit regs" % self.num_axi_regs32()
- return (" `define%(bname)s 'h%(start)08X\n"
- " `define%(bend)s 'h%(end)08X // %(comment)s" % locals(),
+ return (" `define %(bname)s 'h%(start)08X\n"
+ " `define %(bend)s 'h%(end)08X // %(comment)s" % locals(),
offs)
def axi_slave_name(self, name, ifacenum):
sname = self.peripheral.pname(pname).format(count)
ps = "pinmux.peripheral_side.%s" % sname
if typ == 'out' or typ == 'inout':
- ret.append(" rule con_%s%d_%s_out" % (name, count, pname))
+ ret.append(" rule con_%s%d_%s_out;" % (name, count, pname))
fname = self.pinname_out(pname)
+ if not n.startswith('gpio'): # XXX EURGH! horrible hack
+ n_ = "{0}{1}".format(n, count)
+ else:
+ n_ = n
if fname:
if p.get('outen'):
ps_ = ps + '_out'
else:
ps_ = ps
- n_ = "{0}{1}".format(n, count)
ret.append(" {0}({1}.{2});".format(ps_, n_, fname))
fname = None
if p.get('outen'):
fname = self.pinname_outen(pname)
if fname:
- fname = "{0}{1}.{2}".format(n, count, fname)
+ if isinstance(fname, str):
+ fname = "{0}.{1}".format(n_, fname)
fname = self.pinname_tweak(pname, 'outen', fname)
ret.append(" {0}_outen({1});".format(ps, fname))
ret.append(" endrule")
else:
ps_ = ps
ret.append(
- " rule con_%s%d_%s_in" %
+ " rule con_%s%d_%s_in;" %
(name, count, pname))
- ret.append(" {1}.{2}({0});".format(ps_, n, fname))
+ n_ = "{0}{1}".format(n, count)
+ n_ = '{0}.{1}'.format(n_, fname)
+ n_ = self.ifname_tweak(pname, 'in', n_)
+ ret.append(" {1}({0});".format(ps_, n_))
ret.append(" endrule")
return '\n'.join(ret)
def mk_cellconn(self, *args):
return ''
- def mkslow_peripheral(self):
+ def mkslow_peripheral(self, size=0):
return ''
def mksuffix(self, name, i):
def pinname_outen(self, pname):
return ''
+ def ifname_tweak(self, pname, typ, txt):
+ return txt
+
def pinname_tweak(self, pname, typ, txt):
return txt
class uart(PBase):
def slowimport(self):
- return " import Uart16550 :: *;"
+ return " import Uart_bs :: *;\n" + \
+ " import RS232_modified::*;"
def slowifdecl(self):
- return " interface RS232_PHY_Ifc uart{0}_coe;\n" + \
+ return " interface RS232 uart{0}_coe;\n" + \
" method Bit#(1) uart{0}_intr;"
def num_axi_regs32(self):
return 8
- def mkslow_peripheral(self):
- return " Uart16550_AXI4_Lite_Ifc uart{0} <- \n" + \
- " mkUart16550(clocked_by uart_clock,\n" + \
+ def mkslow_peripheral(self, size=0):
+ return " Ifc_Uart_bs uart{0} <- \n" + \
+ " mkUart_bs(clocked_by sp_clock,\n" + \
" reset_by uart_reset, sp_clock, sp_reset);"
def _mk_connection(self, name=None, count=0):
return {'rx': 'coe_rs232.sin'}.get(pname, '')
+class quart(PBase):
+
+ def slowimport(self):
+ return " import Uart16550 :: *;"
+
+ def slowifdecl(self):
+ return " interface RS232_PHY_Ifc quart{0}_coe;\n" + \
+ " method Bit#(1) quart{0}_intr;"
+
+ def num_axi_regs32(self):
+ return 8
+
+ def mkslow_peripheral(self, size=0):
+ return " Uart16550_AXI4_Lite_Ifc quart{0} <- \n" + \
+ " mkUart16550(clocked_by sp_clock,\n" + \
+ " reset_by uart_reset, sp_clock, sp_reset);"
+
+ def _mk_connection(self, name=None, count=0):
+ return "quart{0}.slave_axi_uart"
+
+ def pinname_out(self, pname):
+ return {'tx' : 'coe_rs232.modem_output_stx',
+ 'rts': 'coe_rs232.modem_output_rts',
+ }.get(pname, '')
+
+ def _pinname_in(self, pname):
+ return {'rx': 'coe_rs232.modem_input.srx',
+ 'cts': 'coe_rs232.modem_input.cts'
+ }.get(pname, '')
+
+ def mk_pincon(self, name, count):
+ ret = [PBase.mk_pincon(self, name, count)]
+ size = len(self.peripheral.pinspecs)
+ ret.append(eint_pincon_template.format(size))
+ ret.append(" rule con_%s%d_io_in;" % (name, count))
+ ret.append(" {0}{1}.coe_rs232.modem_input(".format(name, count))
+ for idx, pname in enumerate(['rx', 'cts']):
+ sname = self.peripheral.pname(pname).format(count)
+ ps = "pinmux.peripheral_side.%s" % sname
+ ret.append(" {0},".format(ps))
+ ret.append(" 1'b1,1'b0,1'b1")
+ ret.append(" );")
+ ret.append(" endrule")
+
+ return '\n'.join(ret)
+
+
class rs232(PBase):
def slowimport(self):
def num_axi_regs32(self):
return 2
- def mkslow_peripheral(self):
+ def mkslow_peripheral(self, size=0):
return " //Ifc_Uart_bs uart{0} <-" + \
" // mkUart_bs(clocked_by uart_clock,\n" + \
" // reset_by uart_reset,sp_clock, sp_reset);" +\
def num_axi_regs32(self):
return 8
- def mkslow_peripheral(self):
+ def mkslow_peripheral(self, size=0):
return " I2C_IFC twi{0} <- mkI2CController();"
def _mk_connection(self, name=None, count=0):
'scl': 'out.scl_in'}.get(pname, '')
def pinname_outen(self, pname):
- return {'sda': 'out.sda_outen',
- 'scl': 'out.scl_outen'}.get(pname, '')
+ return {'sda': 'out.sda_out_en',
+ 'scl': 'out.scl_out_en'}.get(pname, '')
def pinname_tweak(self, pname, typ, txt):
if typ == 'outen':
return txt
+class eint(PBase):
+
+ def slowimport(self):
+ size = len(self.peripheral.pinspecs)
+ return " `define NUM_EINTS %d" % size
+
+ def mkslow_peripheral(self, size=0):
+ size = len(self.peripheral.pinspecs)
+ return " Wire#(Bit#(%d)) wr_interrupt <- mkWire();" % size
+
+ def axi_slave_name(self, name, ifacenum):
+ return ''
+
+ def axi_slave_idx(self, idx, name, ifacenum):
+ return ('', 0)
+
+ def axi_addr_map(self, name, ifacenum):
+ return ''
+
+ def ifname_tweak(self, pname, typ, txt):
+ if typ != 'in':
+ return txt
+ print "ifnameweak", pname, typ, txt
+ return "wr_interrupt[{0}] <= ".format(pname)
+
+ def mk_pincon(self, name, count):
+ ret = [PBase.mk_pincon(self, name, count)]
+ size = len(self.peripheral.pinspecs)
+ ret.append(eint_pincon_template.format(size))
+ ret.append(" rule con_%s%d_io_in;" % (name, count))
+ ret.append(" wr_interrupt <= ({")
+ for idx, p in enumerate(self.peripheral.pinspecs):
+ pname = p['name']
+ sname = self.peripheral.pname(pname).format(count)
+ ps = "pinmux.peripheral_side.%s" % sname
+ comma = '' if idx == size - 1 else ','
+ ret.append(" {0}{1}".format(ps, comma))
+ ret.append(" });")
+ ret.append(" endrule")
+
+ return '\n'.join(ret)
+
+
+eint_pincon_template = '''\
+ // TODO: offset i by the number of eints already used
+ for(Integer i=0;i<{0};i=i+ 1)begin
+ rule connect_int_to_plic(wr_interrupt[i]==1);
+ ff_gateway_queue[i].enq(1);
+ plic.ifc_external_irq[i].irq_frm_gateway(True);
+ endrule
+ end
+'''
+
+
+class jtag(PBase):
+
+ def axi_slave_name(self, name, ifacenum):
+ return ''
+
+ def axi_slave_idx(self, idx, name, ifacenum):
+ return ('', 0)
+
+ def axi_addr_map(self, name, ifacenum):
+ return ''
+
+ def slowifdeclmux(self):
+ return " method Action jtag_ms (Bit#(1) in);\n" + \
+ " method Bit#(1) jtag_di;\n" + \
+ " method Action jtag_do (Bit#(1) in);\n" + \
+ " method Action jtag_ck (Bit#(1) in);"
+
+ def slowifinstance(self):
+ return jtag_method_template # bit of a lazy hack this...
+
+jtag_method_template = """\
+ method Action jtag_ms (Bit#(1) in);
+ pinmux.peripheral_side.jtag_ms(in);
+ endmethod
+ method Bit#(1) jtag_di=pinmux.peripheral_side.jtag_di;
+ method Action jtag_do (Bit#(1) in);
+ pinmux.peripheral_side.jtag_do(in);
+ endmethod
+ method Action jtag_ck (Bit#(1) in);
+ pinmux.peripheral_side.jtag_ck(in);
+ endmethod
+"""
+
+class sdmmc(PBase):
+
+ def slowimport(self):
+ return " import sdcard_dummy :: *;"
+
+ def slowifdecl(self):
+ return " interface QSPI_out sd{0}_out;\n" + \
+ " method Bit#(1) sd{0}_isint;"
+
+ def num_axi_regs32(self):
+ return 13
+
+ def mkslow_peripheral(self):
+ return " Ifc_sdcard_dummy sd{0} <- mksdcard_dummy();"
+
+ def _mk_connection(self, name=None, count=0):
+ return "sd{0}.slave"
+
+ def pinname_in(self, pname):
+ return "%s_in" % pname
+
+ def pinname_out(self, pname):
+ if pname.startswith('d'):
+ return "%s_out" % pname
+ return pname
+
+ def pinname_outen(self, pname):
+ if pname.startswith('d'):
+ return "%s_outen" % pname
+
+
+class spi(PBase):
+
+ def slowimport(self):
+ return " import qspi :: *;"
+
+ def slowifdecl(self):
+ return " interface QSPI_out spi{0}_out;\n" + \
+ " method Bit#(1) spi{0}_isint;"
+
+ def num_axi_regs32(self):
+ return 13
+
+ def mkslow_peripheral(self):
+ return " Ifc_qspi spi{0} <- mkqspi();"
+
+ def _mk_connection(self, name=None, count=0):
+ return "spi{0}.slave"
+
+ def pinname_out(self, pname):
+ return {'clk': 'out.clk_o',
+ 'nss': 'out.ncs_o',
+ 'mosi': 'out.io_o[0]',
+ 'miso': 'out.io_o[1]',
+ }.get(pname, '')
+
+ def pinname_outen(self, pname):
+ return {'clk': 1,
+ 'nss': 1,
+ 'mosi': 'out.io_enable[0]',
+ 'miso': 'out.io_enable[1]',
+ }.get(pname, '')
+
+ def mk_pincon(self, name, count):
+ ret = [PBase.mk_pincon(self, name, count)]
+ # special-case for gpio in, store in a temporary vector
+ plen = len(self.peripheral.pinspecs)
+ ret.append(" // XXX NSS and CLK are hard-coded master")
+ ret.append(" // TODO: must add spi slave-mode")
+ ret.append(" // all ins done in one rule from 4-bitfield")
+ ret.append(" rule con_%s%d_io_in;" % (name, count))
+ ret.append(" {0}{1}.out.io_i({{".format(name, count))
+ for idx, pname in enumerate(['mosi', 'miso']):
+ sname = self.peripheral.pname(pname).format(count)
+ ps = "pinmux.peripheral_side.%s_in" % sname
+ ret.append(" {0},".format(ps))
+ ret.append(" 1'b0,1'b0")
+ ret.append(" });")
+ ret.append(" endrule")
+ return '\n'.join(ret)
+
+
class qspi(PBase):
def slowimport(self):
def num_axi_regs32(self):
return 13
- def mkslow_peripheral(self):
+ def mkslow_peripheral(self, size=0):
return " Ifc_qspi qspi{0} <- mkqspi();"
def _mk_connection(self, name=None, count=0):
return "qspi{0}.slave"
+ def pinname_out(self, pname):
+ return {'ck': 'out.clk_o',
+ 'nss': 'out.ncs_o',
+ 'io0': 'out.io_o[0]',
+ 'io1': 'out.io_o[1]',
+ 'io2': 'out.io_o[2]',
+ 'io3': 'out.io_o[3]',
+ }.get(pname, '')
+
+ def pinname_outen(self, pname):
+ return {'ck': 1,
+ 'nss': 1,
+ 'io0': 'out.io_enable[0]',
+ 'io1': 'out.io_enable[1]',
+ 'io2': 'out.io_enable[2]',
+ 'io3': 'out.io_enable[3]',
+ }.get(pname, '')
+
+ def mk_pincon(self, name, count):
+ ret = [PBase.mk_pincon(self, name, count)]
+ # special-case for gpio in, store in a temporary vector
+ plen = len(self.peripheral.pinspecs)
+ ret.append(" // XXX NSS and CLK are hard-coded master")
+ ret.append(" // TODO: must add qspi slave-mode")
+ ret.append(" // all ins done in one rule from 4-bitfield")
+ ret.append(" rule con_%s%d_io_in;" % (name, count))
+ ret.append(" {0}{1}.out.io_i({{".format(name, count))
+ for i, p in enumerate(self.peripheral.pinspecs):
+ typ = p['type']
+ pname = p['name']
+ if not pname.startswith('io'):
+ continue
+ idx = pname[1:]
+ n = name
+ sname = self.peripheral.pname(pname).format(count)
+ ps = "pinmux.peripheral_side.%s_in" % sname
+ comma = '' if i == 5 else ','
+ ret.append(" {0}{1}".format(ps, comma))
+ ret.append(" });")
+ ret.append(" endrule")
+ return '\n'.join(ret)
+
class pwm(PBase):
return " import pwm::*;"
def slowifdecl(self):
- return " interface PWMIO pwm{0}_o;"
+ return " interface PWMIO pwm{0}_io;"
def num_axi_regs32(self):
return 4
- def mkslow_peripheral(self):
- return " Ifc_PWM_bus pwm{0}_bus <- mkPWM_bus(sp_clock);"
+ def mkslow_peripheral(self, size=0):
+ return " Ifc_PWM_bus pwm{0} <- mkPWM_bus(sp_clock);"
def _mk_connection(self, name=None, count=0):
- return "pwm{0}_bus.axi4_slave"
+ return "pwm{0}.axi4_slave"
def pinname_out(self, pname):
return {'out': 'pwm_io.pwm_o'}.get(pname, '')
" import mux::*;\n" + \
" import gpio::*;\n"
- def slowifdecl(self):
- return " interface GPIO_config#({1}) pad_config{0};"
+ def slowifdeclmux(self):
+ size = len(self.peripheral.pinspecs)
+ return " interface GPIO_config#(%d) pad_config{0};" % size
def num_axi_regs32(self):
return 2
GPIO also has a muxer per bank
"""
name = name.upper()
+ mname = 'mux' + name[4:]
+ mname = mname.upper()
+ print "AXIslavenum", name, mname
(ret, x) = PBase.axi_slave_idx(self, idx, name, ifacenum)
- (ret2, x) = PBase.axi_slave_idx(self, idx, "mux", ifacenum)
+ (ret2, x) = PBase.axi_slave_idx(self, idx + 1, mname, ifacenum)
return ("%s\n%s" % (ret, ret2), 2)
- def mkslow_peripheral(self):
- return " MUX#(%(name)s) mux{0} <- mkmux();\n" + \
- " GPIO#(%(name)s) gpio{0} <- mkgpio();" % \
- {'name': self.name}
+ def mkslow_peripheral(self, size=0):
+ print "gpioslow", self.peripheral, dir(self.peripheral)
+ size = len(self.peripheral.pinspecs)
+ return " MUX#(%d) mux{0} <- mkmux();\n" % size + \
+ " GPIO#(%d) gpio{0} <- mkgpio();" % size
def mk_connection(self, count):
print "GPIO mk_conn", self.name, count
return "func.gpio_out[{0}]".format(pname[1:])
def pinname_outen(self, pname):
- return {'sda': 'out.sda_outen',
- 'scl': 'out.scl_outen'}.get(pname, '')
+ return "func.gpio_out_en[{0}]".format(pname[1:])
def mk_pincon(self, name, count):
ret = [PBase.mk_pincon(self, name, count)]
# special-case for gpio in, store in a temporary vector
plen = len(self.peripheral.pinspecs)
- ret.append(" rule con_%s%d_in" % (name, count))
+ ret.append(" rule con_%s%d_in;" % (name, count))
ret.append(" Vector#({0},Bit#(1)) temp;".format(plen))
for p in self.peripheral.pinspecs:
typ = p['type']
if slow:
self.slow = slow(ifacename)
self.slow.peripheral = self
- for fname in ['slowimport', 'slowifdecl', 'mkslow_peripheral',
+ for fname in ['slowimport',
+ 'slowifinstance', 'slowifdecl', 'slowifdeclmux',
+ 'mkslow_peripheral',
'mk_connection', 'mk_cellconn', 'mk_pincon']:
fn = CallFn(self, fname)
setattr(self, fname, types.MethodType(fn, self))
ret.append(self.data[name].slowimport())
return '\n'.join(list(filter(None, ret)))
+ def slowifinstance(self, *args):
+ ret = []
+ for (name, count) in self.ifacecount:
+ #print "slowimport", name, self.data[name].slowimport
+ ret.append(self.data[name].slowifinstance())
+ return '\n'.join(list(filter(None, ret)))
+
+ def slowifdeclmux(self, *args):
+ ret = []
+ for (name, count) in self.ifacecount:
+ for i in range(count):
+ ret.append(self.data[name].slowifdeclmux().format(i, name))
+ return '\n'.join(list(filter(None, ret)))
+
def slowifdecl(self, *args):
ret = []
for (name, count) in self.ifacecount:
#print ("ifc", name, rdef, offs)
ret.append(rdef)
start += offs
- ret.append("typedef %d LastGen_slave_num" % (start - 1))
+ ret.append("typedef %d LastGen_slave_num;" % (start - 1))
decls = '\n'.join(list(filter(None, ret)))
return axi_slave_declarations.format(decls)
for k, v in {'uart': uart,
'rs232': rs232,
'twi': twi,
+ 'quart': quart,
'qspi': qspi,
+ 'spi': spi,
'pwm': pwm,
+ 'eint': eint,
+ 'sd': sdmmc,
+ 'jtag': jtag,
'gpio': gpio
}.items():
if name.startswith(k):
projects / pinmux.git / blobdiff