fix names

[pinmux.git] / src / bsv / peripheral_gen.py

diff --git a/src/bsv/peripheral_gen.py b/src/bsv/peripheral_gen.py
index a4cadb69155d219c47435cd767750d1775631147..d424778ee096163fa0a27ccc18090567d4518c69 100644 (file)
--- a/src/bsv/peripheral_gen.py
+++ b/src/bsv/peripheral_gen.py
@@ -21,8 +21,8 @@ class PBase(object):
         bname = self.axibase(name, ifacenum)
         bend = self.axiend(name, ifacenum)
         comment = "%d 32-bit regs" % self.num_axi_regs32()
-        return ("    `define%(bname)s 'h%(start)08X\n"
-                "    `define%(bend)s  'h%(end)08X // %(comment)s" % locals(),
+        return ("    `define %(bname)s 'h%(start)08X\n"
+                "    `define %(bend)s  'h%(end)08X // %(comment)s" % locals(),
                 offs)
 
     def axi_slave_name(self, name, ifacenum):
@@ -56,14 +56,17 @@ class PBase(object):
             sname = self.peripheral.pname(pname).format(count)
             ps = "pinmux.peripheral_side.%s" % sname
             if typ == 'out' or typ == 'inout':
-                ret.append("    rule con_%s%d_%s_out" % (name, count, pname))
+                ret.append("    rule con_%s%d_%s_out;" % (name, count, pname))
                 fname = self.pinname_out(pname)
                 if fname:
                     if p.get('outen'):
                         ps_ = ps + '_out'
                     else:
                         ps_ = ps
-                    n_ = "{0}{1}".format(n, count)
+                    if not n.startswith('gpio'): # XXX EURGH! horrible hack
+                      n_ = "{0}{1}".format(n, count)
+                    else:
+                      n_ = n
                     ret.append("      {0}({1}.{2});".format(ps_, n_, fname))
                 fname = None
                 if p.get('outen'):
@@ -82,16 +85,17 @@ class PBase(object):
                     else:
                         ps_ = ps
                     ret.append(
-                        "    rule con_%s%d_%s_in" %
+                        "    rule con_%s%d_%s_in;" %
                         (name, count, pname))
-                    ret.append("      {1}.{2}({0});".format(ps_, n, fname))
+                    n_ = "{0}{1}".format(n, count)
+                    ret.append("      {1}.{2}({0});".format(ps_, n_, fname))
                     ret.append("    endrule")
         return '\n'.join(ret)
 
     def mk_cellconn(self, *args):
         return ''
 
-    def mkslow_peripheral(self):
+    def mkslow_peripheral(self, size=0):
         return ''
 
     def mksuffix(self, name, i):
@@ -145,7 +149,7 @@ class uart(PBase):
     def num_axi_regs32(self):
         return 8
 
-    def mkslow_peripheral(self):
+    def mkslow_peripheral(self, size=0):
         return "        Uart16550_AXI4_Lite_Ifc uart{0} <- \n" + \
                "                mkUart16550(clocked_by uart_clock,\n" + \
                "                    reset_by uart_reset, sp_clock, sp_reset);"
@@ -172,7 +176,7 @@ class rs232(PBase):
     def num_axi_regs32(self):
         return 2
 
-    def mkslow_peripheral(self):
+    def mkslow_peripheral(self, size=0):
         return "        //Ifc_Uart_bs uart{0} <-" + \
                "        //       mkUart_bs(clocked_by uart_clock,\n" + \
                "        //          reset_by uart_reset,sp_clock, sp_reset);" +\
@@ -202,7 +206,7 @@ class twi(PBase):
     def num_axi_regs32(self):
         return 8
 
-    def mkslow_peripheral(self):
+    def mkslow_peripheral(self, size=0):
         return "        I2C_IFC twi{0} <- mkI2CController();"
 
     def _mk_connection(self, name=None, count=0):
@@ -217,8 +221,8 @@ class twi(PBase):
                 'scl': 'out.scl_in'}.get(pname, '')
 
     def pinname_outen(self, pname):
-        return {'sda': 'out.sda_outen',
-                'scl': 'out.scl_outen'}.get(pname, '')
+        return {'sda': 'out.sda_out_en',
+                'scl': 'out.scl_out_en'}.get(pname, '')
 
     def pinname_tweak(self, pname, typ, txt):
         if typ == 'outen':
@@ -238,7 +242,7 @@ class qspi(PBase):
     def num_axi_regs32(self):
         return 13
 
-    def mkslow_peripheral(self):
+    def mkslow_peripheral(self, size=0):
         return "        Ifc_qspi qspi{0} <-  mkqspi();"
 
     def _mk_connection(self, name=None, count=0):
@@ -268,9 +272,10 @@ class qspi(PBase):
         plen = len(self.peripheral.pinspecs)
         ret.append("    // XXX NSS and CLK are hard-coded master")
         ret.append("    // TODO: must add qspi slave-mode")
-        ret.append("    rule con_%s%d_io_in" % (name, count))
-        ret.append("       {0}{1}.out.io_i(".format(name, count))
-        for p in self.peripheral.pinspecs:
+        ret.append("    // all ins done in one rule from 4-bitfield")
+        ret.append("    rule con_%s%d_io_in;" % (name, count))
+        ret.append("       {0}{1}.out.io_i({{".format(name, count))
+        for i, p in enumerate(self.peripheral.pinspecs):
             typ = p['type']
             pname = p['name']
             if not pname.startswith('io'):
@@ -279,7 +284,8 @@ class qspi(PBase):
             n = name
             sname = self.peripheral.pname(pname).format(count)
             ps = "pinmux.peripheral_side.%s_in" % sname
-            ret.append("            {0},".format(ps))
+            comma = '' if i == 5 else ','
+            ret.append("            {0}{1}".format(ps, comma))
         ret.append("        });")
         ret.append("    endrule")
         return '\n'.join(ret)
@@ -291,12 +297,12 @@ class pwm(PBase):
         return "        import pwm::*;"
 
     def slowifdecl(self):
-        return "        interface PWMIO pwm{0}_o;"
+        return "        interface PWMIO pwm{0};"
 
     def num_axi_regs32(self):
         return 4
 
-    def mkslow_peripheral(self):
+    def mkslow_peripheral(self, size=0):
         return "        Ifc_PWM_bus pwm{0}_bus <- mkPWM_bus(sp_clock);"
 
     def _mk_connection(self, name=None, count=0):
@@ -324,14 +330,18 @@ class gpio(PBase):
             GPIO also has a muxer per bank
         """
         name = name.upper()
+        mname = 'mux' + name[4:]
+        mname = mname.upper()
+        print "AXIslavenum", name,  mname
         (ret, x) = PBase.axi_slave_idx(self, idx, name, ifacenum)
-        (ret2, x) = PBase.axi_slave_idx(self, idx, "mux", ifacenum)
+        (ret2, x) = PBase.axi_slave_idx(self, idx, mname, ifacenum)
         return ("%s\n%s" % (ret, ret2), 2)
 
-    def mkslow_peripheral(self):
-        return "        MUX#(%(name)s) mux{0} <- mkmux();\n" + \
-               "        GPIO#(%(name)s) gpio{0} <- mkgpio();" % \
-            {'name': self.name}
+    def mkslow_peripheral(self, size=0):
+        print "gpioslow", self.peripheral,  dir(self.peripheral)
+        size = len(self.peripheral.pinspecs)
+        return "        MUX#(%d) mux{0} <- mkmux();\n" % size + \
+               "        GPIO#(%d) gpio{0} <- mkgpio();" % size
 
     def mk_connection(self, count):
         print "GPIO mk_conn", self.name, count
@@ -373,7 +383,7 @@ class gpio(PBase):
         ret = [PBase.mk_pincon(self, name, count)]
         # special-case for gpio in, store in a temporary vector
         plen = len(self.peripheral.pinspecs)
-        ret.append("    rule con_%s%d_in" % (name, count))
+        ret.append("    rule con_%s%d_in;" % (name, count))
         ret.append("       Vector#({0},Bit#(1)) temp;".format(plen))
         for p in self.peripheral.pinspecs:
             typ = p['type']
@@ -495,7 +505,7 @@ class PeripheralInterfaces(object):
                 #print ("ifc", name, rdef, offs)
                 ret.append(rdef)
                 start += offs
-        ret.append("typedef %d LastGen_slave_num" % (start - 1))
+        ret.append("typedef %d LastGen_slave_num;" % (start - 1))
         decls = '\n'.join(list(filter(None, ret)))
         return axi_slave_declarations.format(decls)