add pwm define

[pinmux.git] / src / bsv / pinmux_generator.py

diff --git a/src/bsv/pinmux_generator.py b/src/bsv/pinmux_generator.py
index 7d33d6f387d29e888cdf87d24f0663d7e67c5661..4f452edf72e59ebea0da3f27edf166e93bfa29ab 100644 (file)
--- a/src/bsv/pinmux_generator.py
+++ b/src/bsv/pinmux_generator.py
@@ -73,7 +73,17 @@ def pinmuxgen(pth=None, verify=True):
                     os.path.join(bp, 'Makefile'))
     cwd = os.path.join(cwd, 'bsv_lib')
     for fname in ['AXI4_Lite_Types.bsv', 'Semi_FIFOF.bsv',
-                  'gpio.bsv', 'mux.bsv']:
+                  'gpio.bsv', 'mux.bsv', 
+                  'AXI4_Types.bsv', 'defined_types.bsv', 
+                  'AXI4_Fabric.bsv', 'Uart16550.bsv', 
+                  'AXI4_Lite_Fabric.bsv', 'ConcatReg.bsv', 
+                  'Uart_bs.bsv', 'RS232_modified.bsv', 
+                  'AXI4Lite_AXI4_Bridge.bsv',
+                  'I2C_top.bsv', 'I2C_Defs.bsv', 
+                  'plic.bsv', 'Cur_Cycle.bsv', 
+                  'ClockDiv.bsv', 'axi_addr_generator.bsv', 
+                  'pwm.bsv', 'qspi.bsv', 'qspi.defs', 
+                  ]:
         shutil.copyfile(os.path.join(cwd, fname),
                         os.path.join(bl, fname))
 
@@ -90,10 +100,10 @@ def pinmuxgen(pth=None, verify=True):
     write_bvp(bvp, p, ifaces)
     write_bus(bus, p, ifaces)
     write_instances(idef, p, ifaces)
-    write_slow(slow, slowt, p, ifaces)
+    write_slow(slow, slowt, p, ifaces, iocells)
 
 
-def write_slow(slow, template, p, ifaces):
+def write_slow(slow, template, p, ifaces, iocells):
     """ write out the slow_peripherals.bsv file.
         joins all the peripherals together into one AXI Lite interface
     """
@@ -101,8 +111,17 @@ def write_slow(slow, template, p, ifaces):
         template = bsv_file.read()
     imports = ifaces.slowimport()
     ifdecl = ifaces.slowifdecl()
+    regdef = ifaces.axi_reg_def()
+    slavedecl = ifaces.axi_slave_idx()
+    fnaddrmap = ifaces.axi_addr_map()
+    mkslow = ifaces.mkslow_peripheral()
+    mkcon = ifaces.mk_connection()
+    mkcellcon = ifaces.mk_cellconn()
+    pincon = ifaces.mk_pincon()
     with open(slow, "w") as bsv_file:
-        bsv_file.write(template.format(imports, ifdecl))
+        bsv_file.write(template.format(imports, ifdecl, regdef, slavedecl,
+                                       fnaddrmap, mkslow, mkcon, mkcellcon,
+                                       pincon))
 
 
 def write_bus(bus, p, ifaces):
@@ -354,10 +373,10 @@ def write_bvp(bvp, p, ifaces):
             decl.append(muxdec .format(npins, bank))
             idec.append(gpioifc.format(bank))
             idec.append(muxifc.format(bank))
-        print (dir(ifaces))
-        print (ifaces.items())
-        print (dir(ifaces['gpioa']))
-        print (ifaces['gpioa'].pinspecs)
+        print dir(ifaces)
+        print ifaces.items()
+        print dir(ifaces['gpioa'])
+        print ifaces['gpioa'].pinspecs
         gpiodecl = '\n'.join(decl) + '\n' + '\n'.join(idec)
         gpiocfg = '\n'.join(cfg)
         bsv_file.write(axi4_lite.format(gpiodecl, gpiocfg))
@@ -367,8 +386,29 @@ def write_bvp(bvp, p, ifaces):
 def write_instances(idef, p, ifaces):
     with open(idef, 'w') as bsv_file:
         txt = '''\
-    `define ADDR {0}
-    `define DATA {1}
-    `define USERSPACE 0
+`define ADDR {0}
+`define PADDR {0}
+`define DATA {1}
+`define Reg_width {1}
+`define USERSPACE 0
+
+// TODO: work out if these are needed
+`define PWM_AXI4Lite 
+`define PRFDEPTH 6
+`define VADDR 39
+`define DCACHE_BLOCK_SIZE 4
+`define DCACHE_WORD_SIZE 8
+`define PERFMONITORS                            64
+`define DCACHE_WAYS 4
+`define DCACHE_TAG_BITS 20      // tag_bits = 52
+`define PLIC
+       `define PLICBase                'h0c000000
+       `define PLICEnd         'h10000000
+`define INTERRUPT_PINS 64
+
+`define BAUD_RATE 130
+`ifdef simulate
+  `define BAUD_RATE 5 //130 //
+`endif
 '''
         bsv_file.write(txt.format(p.ADDR_WIDTH, p.DATA_WIDTH))