# copy over template and library files
shutil.copyfile(os.path.join(cwd, 'Makefile.template'),
os.path.join(bp, 'Makefile'))
+ shutil.copyfile(os.path.join(cwd, 'Makefile.peripherals.template'),
+ os.path.join(bp, 'Makefile.peripherals'))
cwd = os.path.join(cwd, 'bsv_lib')
for fname in []:
shutil.copyfile(os.path.join(cwd, fname),
bus = os.path.join(bp, 'busenable.bsv')
pmp = os.path.join(bp, 'pinmux.bsv')
- ptp = os.path.join(bp, 'PinTop.bsv')
bvp = os.path.join(bp, 'bus.bsv')
idef = os.path.join(bp, 'instance_defines.bsv')
slow = os.path.join(bp, 'slow_peripherals.bsv')
slowt = os.path.join(cwd, 'slow_peripherals_template.bsv')
+
slowmf = os.path.join(bp, 'slow_memory_map.bsv')
slowmt = os.path.join(cwd, 'slow_tuple2_template.bsv')
+
+ slowid = os.path.join(bp, 'slow_instance_defines.bsv')
+ slowit = os.path.join(cwd, 'slow_instance_defines_template.bsv')
+
fastmf = os.path.join(bp, 'fast_memory_map.bsv')
fastmt = os.path.join(cwd, 'fast_tuple2_template.bsv')
+
+ fastid = os.path.join(bp, 'fast_instance_defines.bsv')
+ fastit = os.path.join(cwd, 'fast_instance_defines_template.bsv')
+
soc = os.path.join(bp, 'socgen.bsv')
soct = os.path.join(cwd, 'soc_template.bsv')
write_pmp(pmp, p, ifaces, iocells)
- write_ptp(ptp, p, ifaces)
write_bvp(bvp, p, ifaces)
write_bus(bus, p, ifaces)
write_instances(idef, p, ifaces)
- write_slow(slow, slowt, slowmf, slowmt, p, ifaces, iocells)
- write_soc(soc, soct, fastmf, fastmt, p, ifaces, iocells)
-
-
-def write_slow(slow, slowt, slowmf, slowmt, p, ifaces, iocells):
+ write_slow(slow, slowt, slowmf, slowmt, slowid, slowit, p, ifaces, iocells)
+ write_soc(soc, soct, fastmf, fastmt, fastid, fastit, p, ifaces, iocells)
+
+
+def write_slow(
+ slow,
+ slowt,
+ slowmf,
+ slowmt,
+ slowid,
+ slowit,
+ p,
+ ifaces,
+ iocells):
""" write out the slow_peripherals.bsv file.
joins all the peripherals together into one AXI Lite interface
"""
numsloirqs, ifacedef,
inst2, clockcon))
+ with open(slowid, "w") as bsv_file:
+ with open(slowit) as f:
+ slowit = f.read()
+ bsv_file.write(slowit.format(regdef))
+
with open(slowmf, "w") as bsv_file:
with open(slowmt) as f:
slowmt = f.read()
- bsv_file.write(slowmt.format(regdef, slavedecl, fnaddrmap))
+ bsv_file.write(slowmt.format(fnaddrmap, slavedecl))
-def write_soc(soc, soct, fastmf, fastmt, p, ifaces, iocells):
+def write_soc(soc, soct, fastmf, fastmt, fastid, fastit, p, ifaces, iocells):
""" write out the soc.bsv file.
joins all the peripherals together as AXI Masters
"""
clockcon, mkmstcon,
))
+ with open(fastid, "w") as bsv_file:
+ with open(fastit) as f:
+ fastit = f.read()
+ bsv_file.write(fastit.format(regdef))
+
with open(fastmf, "w") as bsv_file:
with open(fastmt) as f:
fastmt = f.read()
- bsv_file.write(fastmt.format(regdef, slavedecl, mastdecl, fnaddrmap))
+ bsv_file.write(fastmt.format(slavedecl, mastdecl, fnaddrmap))
def write_bus(bus, p, ifaces):
with open(pmp, "w") as bsv_file:
bsv_file.write(header)
- cell_bit_width = 'Bit#(%d)' % p.cell_bitwidth
+ bwid_template = 'Bit#(%d)'
bsv_file.write('''\
(*always_ready,always_enabled*)
interface MuxSelectionLines;
// where each IO will have the same number of muxes.''')
for cell in p.muxed_cells:
- bsv_file.write(mux_interface.ifacefmt(cell[0], cell_bit_width))
+ cellnum = cell[0]
+ bitwidth = p.get_muxbitwidth(cellnum)
+ if bitwidth == 0:
+ continue
+ cell_bit_width = bwid_template % bitwidth
+ bsv_file.write(mux_interface.ifacefmt(cellnum, cell_bit_width))
bsv_file.write("\n endinterface\n")
// values for each mux assigned to a CELL
''')
for cell in p.muxed_cells:
- bsv_file.write(mux_interface.wirefmt(
- cell[0], cell_bit_width))
+ cellnum = cell[0]
+ bitwidth = p.get_muxbitwidth(cellnum)
+ if bitwidth == 0:
+ continue
+ cell_bit_width = bwid_template % bitwidth
+ bsv_file.write(mux_interface.wirefmt(cellnum, cell_bit_width))
iocells.wirefmt(bsv_file)
ifaces.wirefmt(bsv_file)
bsv_file.write('''
/*====== This where the muxing starts for each io-cell======*/
Wire#(Bit#(1)) val0<-mkDWire(0); // need a zero
+ Wire#(Bit#(1)) val1<-mkDWire(1); // need a one
''')
bsv_file.write(p.pinmux)
bsv_file.write('''
interface mux_lines = interface MuxSelectionLines
''')
for cell in p.muxed_cells:
+ cellnum = cell[0]
+ bitwidth = p.get_muxbitwidth(cellnum)
+ if bitwidth == 0:
+ continue
+ cell_bit_width = bwid_template % bitwidth
bsv_file.write(
mux_interface.ifacedef(
- cell[0], cell_bit_width))
+ cellnum, cell_bit_width))
bsv_file.write("\n endinterface;")
bsv_file.write('''
# ======================================================================
-def write_ptp(ptp, p, ifaces):
- with open(ptp, 'w') as bsv_file:
- bsv_file.write(copyright + '''
-package PinTop;
- import pinmux::*;
- interface Ifc_PintTop;
- method ActionValue#(Bool) write(Bit#({0}) addr, Bit#({1}) data);
- method Tuple2#(Bool,Bit#({1})) read(Bit#({0}) addr);
- interface PeripheralSide peripheral_side;
- endinterface
-
- module mkPinTop(Ifc_PintTop);
- // instantiate the pin-mux module here
- Ifc_pinmux pinmux <-mkpinmux;
-
- // declare the registers which will be used to mux the IOs
-'''.format(p.ADDR_WIDTH, p.DATA_WIDTH))
-
- cell_bit_width = str(p.cell_bitwidth)
- for cell in p.muxed_cells:
- bsv_file.write('''
- Reg#(Bit#({0})) rg_muxio_{1} <-mkReg(0);'''.format(
- cell_bit_width, cell[0]))
-
- bsv_file.write('''
- // rule to connect the registers to the selection lines of the
- // pin-mux module
- rule connect_selection_registers;''')
-
- for cell in p.muxed_cells:
- bsv_file.write('''
- pinmux.mux_lines.cell{0}_mux(rg_muxio_{0});'''.format(cell[0]))
-
- bsv_file.write('''
- endrule
- // method definitions for the write user interface
- method ActionValue#(Bool) write(Bit#({2}) addr, Bit#({3}) data);
- Bool err=False;
- case (addr[{0}:{1}])'''.format(p.upper_offset, p.lower_offset,
- p.ADDR_WIDTH, p.DATA_WIDTH))
- index = 0
- for cell in p.muxed_cells:
- bsv_file.write('''
- {0}: rg_muxio_{1}<=truncate(data);'''.format(index, cell[0]))
- index = index + 1
-
- bsv_file.write('''
- default: err=True;
- endcase
- return err;
- endmethod''')
-
- bsv_file.write('''
- // method definitions for the read user interface
- method Tuple2#(Bool,Bit#({3})) read(Bit#({2}) addr);
- Bool err=False;
- Bit#(32) data=0;
- case (addr[{0}:{1}])'''.format(p.upper_offset, p.lower_offset,
- p.ADDR_WIDTH, p.DATA_WIDTH))
- index = 0
- for cell in p.muxed_cells:
- bsv_file.write('''
- {0}: data=zeroExtend(rg_muxio_{1});'''.format(index, cell[0]))
- index = index + 1
-
- bsv_file.write('''
- default:err=True;
- endcase
- return tuple2(err,data);
- endmethod
- interface peripheral_side=pinmux.peripheral_side;
- endmodule
-endpackage
-''')
-
-
def write_bvp(bvp, p, ifaces):
# ######## Generate bus transactors ################
gpiocfg = '\t\tinterface GPIO_config#({4}) bank{3}_config;\n' \
decl.append(muxdec .format(npins, bank))
idec.append(gpioifc.format(bank))
idec.append(muxifc.format(bank))
- print dir(ifaces)
- print ifaces.items()
- print dir(ifaces['gpioa'])
- print ifaces['gpioa'].pinspecs
+ print (dir(ifaces))
+ print (ifaces.items())
+ print (dir(ifaces['gpioa']))
+ print (ifaces['gpioa'].pinspecs)
gpiodecl = '\n'.join(decl) + '\n' + '\n'.join(idec)
gpiocfg = '\n'.join(cfg)
bsv_file.write(axi4_lite.format(gpiodecl, gpiocfg))
projects / pinmux.git / blobdiff