getting bsv compile working

[pinmux.git] / src / bsv / pinmux_generator.py

diff --git a/src/bsv/pinmux_generator.py b/src/bsv/pinmux_generator.py
index fcf47f05fe6627c389410d3d8c47f5e26dbfb3a7..9657c95a3b896aff8d615bfc53db124f5f046a1d 100644 (file)
--- a/src/bsv/pinmux_generator.py
+++ b/src/bsv/pinmux_generator.py
@@ -72,7 +72,8 @@ def pinmuxgen(pth=None, verify=True):
     shutil.copyfile(os.path.join(cwd, 'Makefile.template'),
                     os.path.join(bp, 'Makefile'))
     cwd = os.path.join(cwd, 'bsv_lib')
-    for fname in ['AXI4_Lite_Types.bsv', 'Semi_FIFOF.bsv']:
+    for fname in ['AXI4_Lite_Types.bsv', 'Semi_FIFOF.bsv', 
+                  'gpio.bsv',  'mux.bsv']:
         shutil.copyfile(os.path.join(cwd, fname),
                         os.path.join(bl, fname))
 
@@ -116,16 +117,12 @@ def write_pmp(pmp, p, ifaces, iocells):
 
         bsv_file.write('''
 
-      interface PeripheralSide;
-      // declare the interface to the peripherals
-      // Each peripheral's function will be either an input, output
-      // or be bi-directional.  an input field will be an output from the
-      // peripheral and an output field will be an input to the peripheral.
-      // Bi-directional functions also have an output-enable (which
-      // again comes *in* from the peripheral)''')
-        # ==============================================================
+      interface IOCellSide;
+      // declare the interface to the IO cells.
+      // Each IO cell will have 1 input field (output from pin mux)
+      // and an output and out-enable field (input to pinmux)''')
 
-        # == create method definitions for all peripheral interfaces ==#
+        # == create method definitions for all iocell interfaces ==#
         iocells.ifacefmt(bsv_file)
 
         # ===== finish interface definition and start module definition=======
@@ -134,12 +131,16 @@ def write_pmp(pmp, p, ifaces, iocells):
         # ===== io cell definition =======
         bsv_file.write('''
 
-      interface IOCellSide;
-      // declare the interface to the IO cells.
-      // Each IO cell will have 1 input field (output from pin mux)
-      // and an output and out-enable field (input to pinmux)''')
+      interface PeripheralSide;
+      // declare the interface to the peripherals
+      // Each peripheral's function will be either an input, output
+      // or be bi-directional.  an input field will be an output from the
+      // peripheral and an output field will be an input to the peripheral.
+      // Bi-directional functions also have an output-enable (which
+      // again comes *in* from the peripheral)''')
+        # ==============================================================
 
-        # == create method definitions for all iocell interfaces ==#
+        # == create method definitions for all peripheral interfaces ==#
         ifaces.ifacefmt(bsv_file)
         bsv_file.write("\n      endinterface\n")
 
@@ -191,6 +192,7 @@ def write_pmp(pmp, p, ifaces, iocells):
         # ========================= Actual pinmuxing ========================#
         bsv_file.write('''
       /*====== This where the muxing starts for each io-cell======*/
+      Wire#(Bit#(1)) val0<-mkDWire(0); // need a zero
 ''')
         bsv_file.write(p.pinmux)
         bsv_file.write('''
@@ -219,7 +221,6 @@ def write_pmp(pmp, p, ifaces, iocells):
         ifaces.ifacedef(bsv_file)
         bsv_file.write("\n     endinterface;")
 
-
         bsv_file.write(footer)
         print("BSV file successfully generated: bsv_src/pinmux.bsv")
         # ======================================================================
@@ -303,6 +304,44 @@ endpackage
 
 def write_bvp(bvp, p, ifaces):
     # ######## Generate bus transactors ################
+    gpiocfg = '\t\tinterface GPIO_config#({4}) bank{3}_config;\n' \
+              '\t\tinterface AXI4_Lite_Slave_IFC#({0},{1},{2}) bank{3}_slave;'
+    muxcfg = '\t\tinterface MUX_config#({4}) muxb{3}_config;\n' \
+        '\t\tinterface AXI4_Lite_Slave_IFC#({0},{1},{2}) muxb{3}_slave;'
+
+    gpiodec = '\tGPIO#({0}) mygpio{1} <- mkgpio();'
+    muxdec = '\tMUX#({0}) mymux{1} <- mkgpio();'
+    gpioifc = '\tinterface bank{0}_config=mygpio{0}.pad_config;\n' \
+              '\tinterface bank{0}A_slave=mygpio{0}.axi_slave;'
+    muxifc = '\tinterface muxb{0}_config=mymux{0}.pad_config;\n' \
+        '\tinterface muxb{0}A_slave=mymux{0}.axi_slave;'
     with open(bvp, 'w') as bsv_file:
-        bsv_file.write(axi4_lite.format(p.ADDR_WIDTH, p.DATA_WIDTH))
+        # assume here that all muxes have a 1:1 gpio
+        cfg = []
+        decl = []
+        idec = []
+        iks = sorted(ifaces.keys())
+        for iname in iks:
+            if not iname.startswith('gpio'):  # TODO: declare other interfaces
+                continue
+            bank = iname[4:]
+            ifc = ifaces[iname]
+            npins = len(ifc.pinspecs)
+            cfg.append(gpiocfg.format(p.ADDR_WIDTH, p.DATA_WIDTH,
+                                      0,  # USERSPACE
+                                      bank, npins))
+            cfg.append(muxcfg.format(p.ADDR_WIDTH, p.DATA_WIDTH,
+                                     0,  # USERSPACE
+                                     bank, npins))
+            decl.append(gpiodec.format(npins, bank))
+            decl.append(muxdec .format(npins, bank))
+            idec.append(gpioifc.format(bank))
+            idec.append(muxifc.format(bank))
+        print dir(ifaces)
+        print ifaces.items()
+        print dir(ifaces['gpioa'])
+        print ifaces['gpioa'].pinspecs
+        gpiodecl = '\n'.join(decl) + '\n' + '\n'.join(idec)
+        gpiocfg = '\n'.join(cfg)
+        bsv_file.write(axi4_lite.format(gpiodecl, gpiocfg))
     # ##################################################