# copy over template and library files
shutil.copyfile(os.path.join(cwd, 'Makefile.template'),
os.path.join(bp, 'Makefile'))
+ shutil.copyfile(os.path.join(cwd, 'Makefile.peripherals.template'),
+ os.path.join(bp, 'Makefile.peripherals'))
cwd = os.path.join(cwd, 'bsv_lib')
for fname in []:
shutil.copyfile(os.path.join(cwd, fname),
idef = os.path.join(bp, 'instance_defines.bsv')
slow = os.path.join(bp, 'slow_peripherals.bsv')
slowt = os.path.join(cwd, 'slow_peripherals_template.bsv')
+
slowmf = os.path.join(bp, 'slow_memory_map.bsv')
slowmt = os.path.join(cwd, 'slow_tuple2_template.bsv')
+
+ slowid = os.path.join(bp, 'slow_instance_defines.bsv')
+ slowit = os.path.join(cwd, 'slow_instance_defines_template.bsv')
+
fastmf = os.path.join(bp, 'fast_memory_map.bsv')
fastmt = os.path.join(cwd, 'fast_tuple2_template.bsv')
+
soc = os.path.join(bp, 'socgen.bsv')
soct = os.path.join(cwd, 'soc_template.bsv')
write_bvp(bvp, p, ifaces)
write_bus(bus, p, ifaces)
write_instances(idef, p, ifaces)
- write_slow(slow, slowt, slowmf, slowmt, p, ifaces, iocells)
+ write_slow(slow, slowt, slowmf, slowmt, slowid, slowit, p, ifaces, iocells)
write_soc(soc, soct, fastmf, fastmt, p, ifaces, iocells)
-def write_slow(slow, slowt, slowmf, slowmt, p, ifaces, iocells):
+def write_slow(slow, slowt, slowmf, slowmt, slowid, slowit, p, ifaces, iocells):
""" write out the slow_peripherals.bsv file.
joins all the peripherals together into one AXI Lite interface
"""
numsloirqs, ifacedef,
inst2, clockcon))
+ with open(slowid, "w") as bsv_file:
+ with open(slowit) as f:
+ slowit = f.read()
+ bsv_file.write(slowit.format(regdef))
+
with open(slowmf, "w") as bsv_file:
with open(slowmt) as f:
slowmt = f.read()
- bsv_file.write(slowmt.format(regdef, slavedecl, fnaddrmap))
+ bsv_file.write(slowmt.format(fnaddrmap, slavedecl))
def write_soc(soc, soct, fastmf, fastmt, p, ifaces, iocells):
for cell in p.muxed_cells:
cellnum = cell[0]
- cell_bit_width = bwid_template % p.get_muxwidth(cellnum)
+ bitwidth = p.get_muxbitwidth(cellnum)
+ if bitwidth == 0:
+ continue
+ cell_bit_width = bwid_template % bitwidth
bsv_file.write(mux_interface.ifacefmt(cellnum, cell_bit_width))
bsv_file.write("\n endinterface\n")
// values for each mux assigned to a CELL
''')
for cell in p.muxed_cells:
- bsv_file.write(mux_interface.wirefmt(
- cell[0], cell_bit_width))
+ cellnum = cell[0]
+ bitwidth = p.get_muxbitwidth(cellnum)
+ if bitwidth == 0:
+ continue
+ cell_bit_width = bwid_template % bitwidth
+ bsv_file.write(mux_interface.wirefmt(cellnum, cell_bit_width))
iocells.wirefmt(bsv_file)
ifaces.wirefmt(bsv_file)
bsv_file.write('''
/*====== This where the muxing starts for each io-cell======*/
Wire#(Bit#(1)) val0<-mkDWire(0); // need a zero
+ Wire#(Bit#(1)) val1<-mkDWire(1); // need a one
''')
bsv_file.write(p.pinmux)
bsv_file.write('''
interface mux_lines = interface MuxSelectionLines
''')
for cell in p.muxed_cells:
+ cellnum = cell[0]
+ bitwidth = p.get_muxbitwidth(cellnum)
+ if bitwidth == 0:
+ continue
+ cell_bit_width = bwid_template % bitwidth
bsv_file.write(
mux_interface.ifacedef(
- cell[0], cell_bit_width))
+ cellnum, cell_bit_width))
bsv_file.write("\n endinterface;")
bsv_file.write('''