add tercel speed-up but missing id for arty a7 at the moment

[ls2.git] / src / ls2.py

diff --git a/src/ls2.py b/src/ls2.py
index 53c379252f4f6d64db3d329704652b4b0c7cc3e6..db1cf375388b198132276e7664100836e7f8f6fa 100644 (file)
--- a/src/ls2.py
+++ b/src/ls2.py
@@ -871,7 +871,7 @@ def build_platform(fpga, firmware):
         clk_freq = 50e6
         dram_clk_freq = 100e6
     if fpga == 'arty_a7':
-        clk_freq = 24e6 # urrr "working" with the QSPI core (25 mhz does not)
+        clk_freq = 23.0e6 # urrr "working" with the QSPI core (25 mhz does not)
     if fpga == 'ulx3s':
         clk_freq = 40.0e6
     if fpga == 'orangecrab':
@@ -1104,6 +1104,10 @@ def build_platform(fpga, firmware):
         #os.environ['NMIGEN_synth_opts'] = '-abc9'
         os.environ['NMIGEN_synth_opts'] = '-nowidelut'
 
+    if toolchain == 'yosys_nextpnr':
+        # add --seed 2 to arty a7 compile-time options
+        os.environ['NMIGEN_nextpnr_opts'] = '--seed 6'
+
     if platform is not None:
         # build and upload it
         if fpga == 'isim':