Remove cloneTypes in favor of autoclonetype (#51)

[sifive-blocks.git] / src / main / scala / devices / gpio / GPIO.scala

diff --git a/src/main/scala/devices/gpio/GPIO.scala b/src/main/scala/devices/gpio/GPIO.scala
index 4884227c49027a712bba6d6951cce768c1e356f1..a1b166f6694fa2fe64528b03cb3ff03dd8add8e1 100644 (file)
--- a/src/main/scala/devices/gpio/GPIO.scala
+++ b/src/main/scala/devices/gpio/GPIO.scala
@@ -2,11 +2,13 @@
 package sifive.blocks.devices.gpio
 
 import Chisel._
+import chisel3.experimental.MultiIOModule
 import sifive.blocks.devices.pinctrl.{PinCtrl, Pin, BasePin, EnhancedPin, EnhancedPinCtrl}
 import freechips.rocketchip.config.Parameters
+import freechips.rocketchip.util.SynchronizerShiftReg
 import freechips.rocketchip.regmapper._
 import freechips.rocketchip.tilelink._
-import freechips.rocketchip.util.{AsyncResetRegVec, GenericParameterizedBundle}
+import freechips.rocketchip.util.AsyncResetRegVec
 
 case class GPIOParams(address: BigInt, width: Int, includeIOF: Boolean = false)
 
@@ -34,6 +36,14 @@ object IOFCtrl {
 // for the IOF
 class IOFPin extends Pin {
   val o  = new IOFCtrl().asOutput
+
+  def default(): Unit = {
+    this.o.oval  := Bool(false)
+    this.o.oe    := Bool(false)
+    this.o.ie    := Bool(false)
+    this.o.valid := Bool(false)
+  }
+
   def inputPin(pue: Bool = Bool(false) /*ignored*/): Bool = {
     this.o.oval := Bool(false)
     this.o.oe   := Bool(false)
@@ -53,7 +63,7 @@ class IOFPin extends Pin {
 
 // Connect both the i and o side of the pin,
 // and drive the valid signal for the IOF.
-object GPIOPinToIOF {
+object BasePinToIOF {
   def apply(pin: BasePin, iof: IOFPin): Unit = {
     iof <> pin
     iof.o.valid := Bool(true)
@@ -65,7 +75,7 @@ object GPIOPinToIOF {
 // level, and we have to do the pinmux
 // outside of RocketChipTop.
 
-class GPIOPortIO(c: GPIOParams) extends GenericParameterizedBundle(c) {
+class GPIOPortIO(private val c: GPIOParams) extends Bundle {
   val pins = Vec(c.width, new EnhancedPin())
   val iof_0 = if (c.includeIOF) Some(Vec(c.width, new IOFPin).flip) else None
   val iof_1 = if (c.includeIOF) Some(Vec(c.width, new IOFPin).flip) else None
@@ -74,11 +84,11 @@ class GPIOPortIO(c: GPIOParams) extends GenericParameterizedBundle(c) {
 // It would be better if the IOF were here and
 // we could do the pinmux inside.
 trait HasGPIOBundleContents extends Bundle {
-  val params: GPIOParams
+  def params: GPIOParams
   val port = new GPIOPortIO(params)
 }
 
-trait HasGPIOModuleContents extends Module with HasRegMap {
+trait HasGPIOModuleContents extends MultiIOModule with HasRegMap {
   val io: HasGPIOBundleContents
   val params: GPIOParams
   val c = params
@@ -98,7 +108,7 @@ trait HasGPIOModuleContents extends Module with HasRegMap {
   // Synchronize Input to get valueReg
   val inVal = Wire(UInt(0, width=c.width))
   inVal := Vec(io.port.pins.map(_.i.ival)).asUInt
-  val inSyncReg  = ShiftRegister(inVal, 3)
+  val inSyncReg  = SynchronizerShiftReg(inVal, 3, Some("inSyncReg"))
   val valueReg   = Reg(init = UInt(0, c.width), next = inSyncReg)
 
   // Interrupt Configuration
@@ -158,10 +168,10 @@ trait HasGPIOModuleContents extends Module with HasRegMap {
   val swPinCtrl = Wire(Vec(c.width, new EnhancedPinCtrl()))
 
   // This strips off the valid.
-  val iof0Ctrl = Wire(Vec(c.width, new EnhancedPinCtrl()))
-  val iof1Ctrl = Wire(Vec(c.width, new EnhancedPinCtrl()))
+  val iof0Ctrl = Wire(Vec(c.width, new IOFCtrl()))
+  val iof1Ctrl = Wire(Vec(c.width, new IOFCtrl()))
 
-  val iofCtrl = Wire(Vec(c.width, new EnhancedPinCtrl()))
+  val iofCtrl = Wire(Vec(c.width, new IOFCtrl()))
   val iofPlusSwPinCtrl = Wire(Vec(c.width, new EnhancedPinCtrl()))
 
   for (pin <- 0 until c.width) {