package sifive.blocks.devices.gpio
import Chisel._
+import chisel3.experimental.MultiIOModule
import sifive.blocks.devices.pinctrl.{PinCtrl, Pin, BasePin, EnhancedPin, EnhancedPinCtrl}
import freechips.rocketchip.config.Parameters
import freechips.rocketchip.util.SynchronizerShiftReg
import freechips.rocketchip.regmapper._
import freechips.rocketchip.tilelink._
-import freechips.rocketchip.util.{AsyncResetRegVec, GenericParameterizedBundle}
+import freechips.rocketchip.util.AsyncResetRegVec
case class GPIOParams(address: BigInt, width: Int, includeIOF: Boolean = false)
// level, and we have to do the pinmux
// outside of RocketChipTop.
-class GPIOPortIO(c: GPIOParams) extends GenericParameterizedBundle(c) {
+class GPIOPortIO(private val c: GPIOParams) extends Bundle {
val pins = Vec(c.width, new EnhancedPin())
val iof_0 = if (c.includeIOF) Some(Vec(c.width, new IOFPin).flip) else None
val iof_1 = if (c.includeIOF) Some(Vec(c.width, new IOFPin).flip) else None
val port = new GPIOPortIO(params)
}
-trait HasGPIOModuleContents extends Module with HasRegMap {
+trait HasGPIOModuleContents extends MultiIOModule with HasRegMap {
val io: HasGPIOBundleContents
val params: GPIOParams
val c = params
val swPinCtrl = Wire(Vec(c.width, new EnhancedPinCtrl()))
// This strips off the valid.
- val iof0Ctrl = Wire(Vec(c.width, new EnhancedPinCtrl()))
- val iof1Ctrl = Wire(Vec(c.width, new EnhancedPinCtrl()))
+ val iof0Ctrl = Wire(Vec(c.width, new IOFCtrl()))
+ val iof1Ctrl = Wire(Vec(c.width, new IOFCtrl()))
- val iofCtrl = Wire(Vec(c.width, new EnhancedPinCtrl()))
+ val iofCtrl = Wire(Vec(c.width, new IOFCtrl()))
val iofPlusSwPinCtrl = Wire(Vec(c.width, new EnhancedPinCtrl()))
for (pin <- 0 until c.width) {