package sifive.blocks.devices.gpio
import Chisel._
+import config.Field
import diplomacy.LazyModule
-import rocketchip.{TopNetwork,TopNetworkModule}
+import rocketchip.{
+ HasTopLevelNetworks,
+ HasTopLevelNetworksBundle,
+ HasTopLevelNetworksModule
+}
import uncore.tilelink2.TLFragmenter
+import util.HeterogeneousBag
+
+case object PeripheryGPIOKey extends Field[Seq[GPIOParams]]
-trait PeripheryGPIO {
- this: TopNetwork { val gpioConfig: GPIOConfig } =>
- val gpio = LazyModule(new TLGPIO(gpioConfig))
- gpio.node := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
- intBus.intnode := gpio.intnode
+trait HasPeripheryGPIO extends HasTopLevelNetworks {
+ val gpioParams = p(PeripheryGPIOKey)
+ val gpio = gpioParams map {params =>
+ val gpio = LazyModule(new TLGPIO(peripheryBusBytes, params))
+ gpio.node := TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node)
+ intBus.intnode := gpio.intnode
+ gpio
+ }
}
-trait PeripheryGPIOBundle {
- this: { val gpioConfig: GPIOConfig } =>
- val gpio = new GPIOPortIO(gpioConfig)
+trait HasPeripheryGPIOBundle extends HasTopLevelNetworksBundle {
+ val outer: HasPeripheryGPIO
+ val gpio = HeterogeneousBag(outer.gpioParams.map(new GPIOPortIO(_)))
}
-trait PeripheryGPIOModule {
- this: TopNetworkModule {
- val gpioConfig: GPIOConfig
- val outer: PeripheryGPIO
- val io: PeripheryGPIOBundle
- } =>
- io.gpio <> outer.gpio.module.io.port
+trait HasPeripheryGPIOModule extends HasTopLevelNetworksModule {
+ val outer: HasPeripheryGPIO
+ val io: HasPeripheryGPIOBundle
+ (io.gpio zip outer.gpio) foreach { case (io, device) =>
+ io <> device.module.io.port
+ }
}