periphery: peripherals now in coreplex (#26)

[sifive-blocks.git] / src / main / scala / devices / i2c / I2CPeriphery.scala

diff --git a/src/main/scala/devices/i2c/I2CPeriphery.scala b/src/main/scala/devices/i2c/I2CPeriphery.scala
index fc62c6bd5dc21c9945169bb0b723a3b416167005..1cc927f46adf7b5243c76d31c23c0f703e4ac295 100644 (file)
--- a/src/main/scala/devices/i2c/I2CPeriphery.scala
+++ b/src/main/scala/devices/i2c/I2CPeriphery.scala
@@ -2,19 +2,18 @@
 package sifive.blocks.devices.i2c
 
 import Chisel._
-import config.Field
-import diplomacy.{LazyModule,LazyMultiIOModuleImp}
-import rocketchip.{HasSystemNetworks}
-import uncore.tilelink2.TLFragmenter
+import freechips.rocketchip.config.Field
+import freechips.rocketchip.coreplex.{HasPeripheryBus, HasInterruptBus}
+import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
 
 case object PeripheryI2CKey extends Field[Seq[I2CParams]]
 
-trait HasPeripheryI2C extends HasSystemNetworks {
+trait HasPeripheryI2C extends HasPeripheryBus {
   val i2cParams = p(PeripheryI2CKey)
   val i2c = i2cParams map { params =>
-    val i2c = LazyModule(new TLI2C(peripheryBusBytes, params))
-    i2c.node := TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node)
-    intBus.intnode := i2c.intnode
+    val i2c = LazyModule(new TLI2C(pbus.beatBytes, params))
+    i2c.node := pbus.toVariableWidthSlaves
+    ibus.fromSync := i2c.intnode
     i2c
   }
 }