package sifive.blocks.devices.i2c
import Chisel._
-import config.Field
-import diplomacy.{LazyModule,LazyMultiIOModuleImp}
-import rocketchip.{HasSystemNetworks}
-import uncore.tilelink2.TLFragmenter
+import freechips.rocketchip.config.Field
+import freechips.rocketchip.diplomacy.{LazyModule,LazyMultiIOModuleImp}
+import freechips.rocketchip.chip.{HasSystemNetworks}
+import freechips.rocketchip.tilelink.TLFragmenter
case object PeripheryI2CKey extends Field[Seq[I2CParams]]
}
trait HasPeripheryI2CBundle {
- val i2cs: Vec[I2CPort]
-
- def toGPIOPins(dummy: Int = 1): Seq[I2CGPIOPort] = i2cs.map { i =>
- val pin = Module(new I2CGPIOPort)
- pin.io.i2c <> i
- pin
- }
+ val i2c: Vec[I2CPort]
}
trait HasPeripheryI2CModuleImp extends LazyMultiIOModuleImp with HasPeripheryI2CBundle {
val outer: HasPeripheryI2C
- val i2cs = IO(Vec(outer.i2cParams.size, new I2CPort))
+ val i2c = IO(Vec(outer.i2cParams.size, new I2CPort))
- (i2cs zip outer.i2c).foreach { case (io, device) =>
+ (i2c zip outer.i2c).foreach { case (io, device) =>
io <> device.module.io.port
}
}