More Peripheral-to-pins cleanups

[sifive-blocks.git] / src / main / scala / devices / i2c / I2CPeriphery.scala

diff --git a/src/main/scala/devices/i2c/I2CPeriphery.scala b/src/main/scala/devices/i2c/I2CPeriphery.scala
index d9c3ff4085d3aa515f1dcc309dd6eed5d77d8002..fc62c6bd5dc21c9945169bb0b723a3b416167005 100644 (file)
--- a/src/main/scala/devices/i2c/I2CPeriphery.scala
+++ b/src/main/scala/devices/i2c/I2CPeriphery.scala
@@ -22,10 +22,10 @@ trait HasPeripheryI2C extends HasSystemNetworks {
 trait HasPeripheryI2CBundle {
   val i2cs: Vec[I2CPort]
 
-  def toGPIOPins(syncStages: Int = 0): Seq[I2CGPIOPort] = i2cs.map { i =>
-    val pin = Module(new I2CGPIOPort(syncStages))
-    pin.io.i2c <> i
-    pin
+  def I2CtoGPIOPins(syncStages: Int = 0): Seq[I2CPinsIO] = i2cs.map { i =>
+    val pins = Module(new I2CGPIOPort(syncStages))
+    pins.io.i2c <> i
+    pins.io.pins
   }
 }