periphery: bus api update (#50)

[sifive-blocks.git] / src / main / scala / devices / mockaon / MockAONPeriphery.scala

diff --git a/src/main/scala/devices/mockaon/MockAONPeriphery.scala b/src/main/scala/devices/mockaon/MockAONPeriphery.scala
index b20bee24e35cc3abc6b2a676ace53ca6dde3f590..0aa4aa781aff1b70ca713ce980e2bb0b6b6172b4 100644 (file)
--- a/src/main/scala/devices/mockaon/MockAONPeriphery.scala
+++ b/src/main/scala/devices/mockaon/MockAONPeriphery.scala
@@ -3,26 +3,23 @@ package sifive.blocks.devices.mockaon
 
 import Chisel._
 import freechips.rocketchip.config.Field
-import freechips.rocketchip.util.SynchronizerShiftReg
-import freechips.rocketchip.coreplex.{HasPeripheryBus, HasInterruptBus}
 import freechips.rocketchip.devices.debug.HasPeripheryDebug
-import freechips.rocketchip.devices.tilelink.HasPeripheryClint
-import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
-import freechips.rocketchip.tilelink.{IntXing, TLAsyncCrossingSource}
-import freechips.rocketchip.util.ResetCatchAndSync
+import freechips.rocketchip.devices.tilelink.HasPeripheryCLINT
+import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
+import freechips.rocketchip.interrupts._
+import freechips.rocketchip.subsystem.BaseSubsystem
+import freechips.rocketchip.tilelink.{TLAsyncCrossingSource}
+import freechips.rocketchip.util.{ResetCatchAndSync, SynchronizerShiftReg}
 
 case object PeripheryMockAONKey extends Field[MockAONParams]
 
-trait HasPeripheryMockAON extends HasPeripheryBus
-    with HasInterruptBus
-    with HasPeripheryClint
-    with HasPeripheryDebug {
+trait HasPeripheryMockAON extends HasPeripheryCLINT with HasPeripheryDebug { this: BaseSubsystem =>
   // We override the clock & Reset here so that all synchronizers, etc
   // are in the proper clock domain.
   val mockAONParams= p(PeripheryMockAONKey)
   val aon = LazyModule(new MockAONWrapper(pbus.beatBytes, mockAONParams))
-  aon.node := pbus.toAsyncVariableWidthSlaves(sync = 3)
-  ibus.fromAsync := aon.intnode
+  pbus.toVariableWidthSlave(Some("aon")) { aon.node := TLAsyncCrossingSource() }
+  ibus.fromSync := IntSyncCrossingSink() := aon.intnode
 }
 
 trait HasPeripheryMockAONBundle {
@@ -32,7 +29,7 @@ trait HasPeripheryMockAONBundle {
   }
 }
 
-trait HasPeripheryMockAONModuleImp extends LazyMultiIOModuleImp with HasPeripheryMockAONBundle {
+trait HasPeripheryMockAONModuleImp extends LazyModuleImp with HasPeripheryMockAONBundle {
   val outer: HasPeripheryMockAON
   val aon = IO(new MockAONWrapperBundle)