Remove cloneTypes in favor of autoclonetype (#51)

[sifive-blocks.git] / src / main / scala / devices / pwm / PWMPeriphery.scala

diff --git a/src/main/scala/devices/pwm/PWMPeriphery.scala b/src/main/scala/devices/pwm/PWMPeriphery.scala
index ff5b6bbe1a20aff22e859e3a27c5b65f1ad0a430..cc2c6edadf5baa34181d30a3ec42747fb6186f07 100644 (file)
--- a/src/main/scala/devices/pwm/PWMPeriphery.scala
+++ b/src/main/scala/devices/pwm/PWMPeriphery.scala
@@ -3,37 +3,24 @@ package sifive.blocks.devices.pwm
 
 import Chisel._
 import freechips.rocketchip.config.Field
-import freechips.rocketchip.coreplex.{HasPeripheryBus, HasInterruptBus}
-import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
+import freechips.rocketchip.subsystem.BaseSubsystem
+import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
 import freechips.rocketchip.util.HeterogeneousBag
 import sifive.blocks.devices.pinctrl.{Pin}
 
 class PWMPortIO(val c: PWMParams) extends Bundle {
   val port = Vec(c.ncmp, Bool()).asOutput
-  override def cloneType: this.type = new PWMPortIO(c).asInstanceOf[this.type]
 }
 
-class PWMPins[T <: Pin] (pingen: ()=> T, val c: PWMParams) extends Bundle {
-
-  val pwm: Vec[T] = Vec(c.ncmp, pingen())
-
-  override def cloneType: this.type =
-    this.getClass.getConstructors.head.newInstance(pingen, c).asInstanceOf[this.type]
-
-  def fromPWMPort(port: PWMPortIO) {
-    (pwm zip port.port)  foreach {case (pin, port) =>
-      pin.outputPin(port)
-    }
-  }
-}
 
 case object PeripheryPWMKey extends Field[Seq[PWMParams]]
 
-trait HasPeripheryPWM extends HasPeripheryBus with HasInterruptBus {
+trait HasPeripheryPWM { this: BaseSubsystem =>
   val pwmParams = p(PeripheryPWMKey)
-  val pwms = pwmParams map { params =>
-    val pwm = LazyModule(new TLPWM(pbus.beatBytes, params))
-    pwm.node := pbus.toVariableWidthSlaves
+  val pwms = pwmParams.zipWithIndex.map { case(params, i) =>
+    val name = Some(s"pwm_$i")
+    val pwm = LazyModule(new TLPWM(pbus.beatBytes, params)).suggestName(name)
+    pbus.toVariableWidthSlave(name) { pwm.node }
     ibus.fromSync := pwm.intnode
     pwm
   }
@@ -44,7 +31,7 @@ trait HasPeripheryPWMBundle {
 
 }
 
-trait HasPeripheryPWMModuleImp extends LazyMultiIOModuleImp with HasPeripheryPWMBundle {
+trait HasPeripheryPWMModuleImp extends LazyModuleImp with HasPeripheryPWMBundle {
   val outer: HasPeripheryPWM
   val pwm = IO(HeterogeneousBag(outer.pwmParams.map(new PWMPortIO(_))))