import Chisel._
import freechips.rocketchip.config.Field
-import freechips.rocketchip.diplomacy.{LazyModule,LazyMultiIOModuleImp}
-import freechips.rocketchip.chip.HasSystemNetworks
-import freechips.rocketchip.tilelink.TLFragmenter
+import freechips.rocketchip.subsystem.BaseSubsystem
+import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
import freechips.rocketchip.util.HeterogeneousBag
-import sifive.blocks.devices.pinctrl.{PinCtrl, Pin}
+import sifive.blocks.devices.pinctrl.{Pin}
class PWMPortIO(val c: PWMParams) extends Bundle {
val port = Vec(c.ncmp, Bool()).asOutput
override def cloneType: this.type = new PWMPortIO(c).asInstanceOf[this.type]
}
-class PWMPins[T <: Pin] (pingen: ()=> T, val c: PWMParams) extends Bundle {
-
- val pwm: Vec[T] = Vec(c.ncmp, pingen())
-
- override def cloneType: this.type =
- this.getClass.getConstructors.head.newInstance(pingen, c).asInstanceOf[this.type]
-
- def fromPWMPort(port: PWMPortIO) {
- (pwm zip port.port) foreach {case (pin, port) =>
- pin.outputPin(port)
- }
- }
-}
case object PeripheryPWMKey extends Field[Seq[PWMParams]]
-trait HasPeripheryPWM extends HasSystemNetworks {
+trait HasPeripheryPWM { this: BaseSubsystem =>
val pwmParams = p(PeripheryPWMKey)
- val pwms = pwmParams map { params =>
- val pwm = LazyModule(new TLPWM(peripheryBusBytes, params))
- pwm.node := TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node)
- intBus.intnode := pwm.intnode
+ val pwms = pwmParams.zipWithIndex.map { case(params, i) =>
+ val name = Some(s"pwm_$i")
+ val pwm = LazyModule(new TLPWM(pbus.beatBytes, params)).suggestName(name)
+ pbus.toVariableWidthSlave(name) { pwm.node }
+ ibus.fromSync := pwm.intnode
pwm
}
}
}
-trait HasPeripheryPWMModuleImp extends LazyMultiIOModuleImp with HasPeripheryPWMBundle {
+trait HasPeripheryPWMModuleImp extends LazyModuleImp with HasPeripheryPWMBundle {
val outer: HasPeripheryPWM
val pwm = IO(HeterogeneousBag(outer.pwmParams.map(new PWMPortIO(_))))