Refactor package hierarchy.

[sifive-blocks.git] / src / main / scala / devices / pwm / PWMPeriphery.scala

diff --git a/src/main/scala/devices/pwm/PWMPeriphery.scala b/src/main/scala/devices/pwm/PWMPeriphery.scala
index 992699fa6c907e949a3e168eb7913787ed02b0bd..ea17f8a572d46cbe0b0812666cdd993b34c440c3 100644 (file)
--- a/src/main/scala/devices/pwm/PWMPeriphery.scala
+++ b/src/main/scala/devices/pwm/PWMPeriphery.scala
@@ -2,23 +2,24 @@
 package sifive.blocks.devices.pwm
 
 import Chisel._
-import config._
-import diplomacy.LazyModule
-import rocketchip.{TopNetwork,TopNetworkModule}
-import uncore.tilelink2.TLFragmenter
+import freechips.rocketchip.config.Field
+import freechips.rocketchip.diplomacy.{LazyModule,LazyMultiIOModuleImp}
+import freechips.rocketchip.chip.HasSystemNetworks
+import freechips.rocketchip.tilelink.TLFragmenter
+import freechips.rocketchip.util.HeterogeneousBag
 
 import sifive.blocks.devices.gpio._
 
-class PWMPortIO(c: PWMBundleConfig)(implicit p: Parameters) extends Bundle {
+class PWMPortIO(val c: PWMParams) extends Bundle {
   val port = Vec(c.ncmp, Bool()).asOutput
   override def cloneType: this.type = new PWMPortIO(c).asInstanceOf[this.type]
 }
 
-class PWMPinsIO(c: PWMBundleConfig)(implicit p: Parameters) extends Bundle {
+class PWMPinsIO(val c: PWMParams) extends Bundle {
   val pwm = Vec(c.ncmp, new GPIOPin)
 }
 
-class PWMGPIOPort(c: PWMBundleConfig)(implicit p: Parameters) extends Module {
+class PWMGPIOPort(val c: PWMParams) extends Module {
   val io = new Bundle {
     val pwm = new PWMPortIO(c).flip()
     val pins = new PWMPinsIO(c)
@@ -27,32 +28,33 @@ class PWMGPIOPort(c: PWMBundleConfig)(implicit p: Parameters) extends Module {
   GPIOOutputPinCtrl(io.pins.pwm, io.pwm.port.asUInt)
 }
 
-trait PeripheryPWM {
-  this: TopNetwork { val pwmConfigs: Seq[PWMConfig] } =>
+case object PeripheryPWMKey extends Field[Seq[PWMParams]]
 
-  val pwmDevices = (pwmConfigs.zipWithIndex) map { case (c, i) =>
-    val pwm = LazyModule(new TLPWM(c) { override lazy val  valName = Some(s"pwm$i") })
-    pwm.node := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
+trait HasPeripheryPWM extends HasSystemNetworks {
+  val pwmParams = p(PeripheryPWMKey)
+  val pwms = pwmParams map { params =>
+    val pwm = LazyModule(new TLPWM(peripheryBusBytes, params))
+    pwm.node := TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node)
     intBus.intnode := pwm.intnode
     pwm
   }
 }
 
-trait PeripheryPWMBundle {
-  this: {
-    val p: Parameters
-    val pwmConfigs: Seq[PWMConfig]
-  } =>
-  val pwm_bc = pwmConfigs.map(_.bc).reduce(_.union(_))
-  val pwms = Vec(pwmConfigs.size, new PWMPortIO(pwm_bc)(p))
+trait HasPeripheryPWMBundle {
+  val pwms: HeterogeneousBag[PWMPortIO]
+
+  def PWMtoGPIOPins(dummy: Int = 1): Seq[PWMPinsIO] = pwms.map { p =>
+    val pins = Module(new PWMGPIOPort(p.c))
+    pins.io.pwm <> p
+    pins.io.pins
+  }
 }
 
-trait PeripheryPWMModule {
-  this: TopNetworkModule {
-    val outer: PeripheryPWM
-    val io: PeripheryPWMBundle
-  } =>
-  (io.pwms.zipWithIndex zip outer.pwmDevices) foreach { case ((io, i), device) =>
+trait HasPeripheryPWMModuleImp extends LazyMultiIOModuleImp with HasPeripheryPWMBundle {
+  val outer: HasPeripheryPWM
+  val pwms = IO(HeterogeneousBag(outer.pwmParams.map(new PWMPortIO(_))))
+
+  (pwms zip outer.pwms) foreach { case (io, device) =>
     io.port := device.module.io.gpio
   }
 }