periphery: peripherals now in coreplex (#26)

[sifive-blocks.git] / src / main / scala / devices / spi / SPIPeriphery.scala

diff --git a/src/main/scala/devices/spi/SPIPeriphery.scala b/src/main/scala/devices/spi/SPIPeriphery.scala
index bd77259dad2577e205c3e13b371c0699f88c14c2..37151bd06cda84a0e8a5f6b9178824418c024e64 100644 (file)
--- a/src/main/scala/devices/spi/SPIPeriphery.scala
+++ b/src/main/scala/devices/spi/SPIPeriphery.scala
@@ -2,20 +2,20 @@
 package sifive.blocks.devices.spi
 
 import Chisel._
-import config.Field
-import diplomacy.{LazyModule,LazyMultiIOModuleImp}
-import rocketchip.HasSystemNetworks
-import uncore.tilelink2.{TLFragmenter,TLWidthWidget}
-import util.HeterogeneousBag
+import freechips.rocketchip.config.Field
+import freechips.rocketchip.coreplex.{HasPeripheryBus, HasInterruptBus}
+import freechips.rocketchip.diplomacy.{LazyModule,LazyMultiIOModuleImp}
+import freechips.rocketchip.tilelink.{TLFragmenter}
+import freechips.rocketchip.util.HeterogeneousBag
 
 case object PeripherySPIKey extends Field[Seq[SPIParams]]
 
-trait HasPeripherySPI extends HasSystemNetworks {
+trait HasPeripherySPI extends HasPeripheryBus with HasInterruptBus {
   val spiParams = p(PeripherySPIKey)  
   val spis = spiParams map { params =>
-    val spi = LazyModule(new TLSPI(peripheryBusBytes, params))
-    spi.rnode := TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node)
-    intBus.intnode := spi.intnode
+    val spi = LazyModule(new TLSPI(pbus.beatBytes, params))
+    spi.rnode := pbus.toVariableWidthSlaves
+    ibus.fromSync := spi.intnode
     spi
   }
 }
@@ -23,10 +23,10 @@ trait HasPeripherySPI extends HasSystemNetworks {
 trait HasPeripherySPIBundle {
   val spis: HeterogeneousBag[SPIPortIO]
 
-  def SPItoGPIOPins(sync_stages: Int = 0): Seq[SPIGPIOPort] = spis.map { s =>
-    val pin = Module(new SPIGPIOPort(s.c, sync_stages))
-    pin.io.spi <> s
-    pin
+  def SPItoGPIOPins(syncStages: Int = 0): Seq[SPIPinsIO] = spis.map { s =>
+    val pins = Module(new SPIGPIOPort(s.c, syncStages))
+    pins.io.spi <> s
+    pins.io.pins
   }
 }
 
@@ -41,19 +41,28 @@ trait HasPeripherySPIModuleImp extends LazyMultiIOModuleImp with HasPeripherySPI
 
 case object PeripherySPIFlashKey extends Field[Seq[SPIFlashParams]]
 
-trait HasPeripherySPIFlash extends HasSystemNetworks {
+trait HasPeripherySPIFlash extends HasPeripheryBus with HasInterruptBus {
   val spiFlashParams = p(PeripherySPIFlashKey)  
   val qspi = spiFlashParams map { params =>
-    val qspi = LazyModule(new TLSPIFlash(peripheryBusBytes, params))
-    qspi.rnode := TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node)
-    qspi.fnode := TLFragmenter(1, cacheBlockBytes)(TLWidthWidget(peripheryBusBytes)(peripheryBus.node))
-    intBus.intnode := qspi.intnode
+    val qspi = LazyModule(new TLSPIFlash(pbus.beatBytes, params))
+    qspi.rnode := pbus.toVariableWidthSlaves
+    qspi.fnode := TLFragmenter(1, pbus.blockBytes)(pbus.toFixedWidthSlaves)
+    ibus.fromSync := qspi.intnode
     qspi
   }
 }
 
 trait HasPeripherySPIFlashBundle {
   val qspi: HeterogeneousBag[SPIPortIO]
+
+  // It is important for SPIFlash that the syncStages is agreed upon, because
+  // internally it needs to realign the input data to the output SCK.
+  // Therefore, we rely on the syncStages parameter.
+  def SPIFlashtoGPIOPins(syncStages: Int = 0): Seq[SPIPinsIO] = qspi.map { s =>
+    val pins = Module(new SPIGPIOPort(s.c, syncStages))
+    pins.io.spi <> s
+    pins.io.pins
+  }
 }
 
 trait HasPeripherySPIFlashModuleImp extends LazyMultiIOModuleImp with HasPeripherySPIFlashBundle {
@@ -64,4 +73,3 @@ trait HasPeripherySPIFlashModuleImp extends LazyMultiIOModuleImp with HasPeriphe
     io <> device.module.io.port
   }
 }
-