import Chisel._
import freechips.rocketchip.config.Field
-import freechips.rocketchip.coreplex.{HasPeripheryBus, HasInterruptBus}
-import freechips.rocketchip.diplomacy.{LazyModule,LazyMultiIOModuleImp}
-import freechips.rocketchip.tilelink.{TLFragmenter}
+import freechips.rocketchip.subsystem.BaseSubsystem
+import freechips.rocketchip.diplomacy.{LazyModule,LazyModuleImp,BufferParams}
+import freechips.rocketchip.tilelink.{TLFragmenter,TLBuffer}
import freechips.rocketchip.util.HeterogeneousBag
case object PeripherySPIKey extends Field[Seq[SPIParams]]
-trait HasPeripherySPI extends HasPeripheryBus with HasInterruptBus {
+trait HasPeripherySPI { this: BaseSubsystem =>
val spiParams = p(PeripherySPIKey)
- val spis = spiParams map { params =>
- val spi = LazyModule(new TLSPI(pbus.beatBytes, params))
- spi.rnode := pbus.toVariableWidthSlaves
+ val spis = spiParams.zipWithIndex.map { case(params, i) =>
+ val name = Some(s"spi_$i")
+ val spi = LazyModule(new TLSPI(pbus.beatBytes, params)).suggestName(name)
+ pbus.toVariableWidthSlave(name) { spi.rnode }
ibus.fromSync := spi.intnode
spi
}
}
-trait HasPeripherySPIModuleImp extends LazyMultiIOModuleImp with HasPeripherySPIBundle {
+trait HasPeripherySPIModuleImp extends LazyModuleImp with HasPeripherySPIBundle {
val outer: HasPeripherySPI
val spi = IO(HeterogeneousBag(outer.spiParams.map(new SPIPortIO(_))))
case object PeripherySPIFlashKey extends Field[Seq[SPIFlashParams]]
-trait HasPeripherySPIFlash extends HasPeripheryBus with HasInterruptBus {
+trait HasPeripherySPIFlash { this: BaseSubsystem =>
val spiFlashParams = p(PeripherySPIFlashKey)
- val qspis = spiFlashParams map { params =>
+ val qspis = spiFlashParams.zipWithIndex.map { case(params, i) =>
+ val name = Some(s"qspi_$i")
val qspi = LazyModule(new TLSPIFlash(pbus.beatBytes, params))
- qspi.rnode := pbus.toVariableWidthSlaves
- qspi.fnode := TLFragmenter(1, pbus.blockBytes)(pbus.toFixedWidthSlaves)
+ pbus.toVariableWidthSlave(name) { qspi.rnode }
+ qspi.fnode := pbus.toFixedWidthSlave(name) {
+ TLFragmenter(1, pbus.blockBytes) :=
+ TLBuffer(BufferParams(params.fBufferDepth), BufferParams.none)
+ }
ibus.fromSync := qspi.intnode
qspi
}
}
-trait HasPeripherySPIFlashModuleImp extends LazyMultiIOModuleImp with HasPeripherySPIFlashBundle {
+trait HasPeripherySPIFlashModuleImp extends LazyModuleImp with HasPeripherySPIFlashBundle {
val outer: HasPeripherySPIFlash
val qspi = IO(HeterogeneousBag(outer.spiFlashParams.map(new SPIPortIO(_))))