spi: SPIParamsBase param needs to be public

[sifive-blocks.git] / src / main / scala / devices / spi / SPIPeriphery.scala

diff --git a/src/main/scala/devices/spi/SPIPeriphery.scala b/src/main/scala/devices/spi/SPIPeriphery.scala
index f4773a228c7cabf9646381ed4b9cea756be77270..37fe3d9081beff59aa9106bc287b09c6acc952c9 100644 (file)
--- a/src/main/scala/devices/spi/SPIPeriphery.scala
+++ b/src/main/scala/devices/spi/SPIPeriphery.scala
@@ -2,56 +2,66 @@
 package sifive.blocks.devices.spi
 
 import Chisel._
-import diplomacy.LazyModule
-import uncore.tilelink2._
-import rocketchip.{TopNetwork,TopNetworkModule}
-
-trait PeripherySPI {
-  this: TopNetwork { val spiConfigs: Seq[SPIConfig] } =>
-  val spi = (spiConfigs.zipWithIndex) map {case (c, i) =>
-    val spi = LazyModule(new TLSPI(c))
-    spi.rnode := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
-    intBus.intnode := spi.intnode
+import freechips.rocketchip.config.Field
+import freechips.rocketchip.subsystem.BaseSubsystem
+import freechips.rocketchip.diplomacy.{LazyModule,LazyModuleImp,BufferParams}
+import freechips.rocketchip.tilelink.{TLFragmenter,TLBuffer}
+import freechips.rocketchip.util.HeterogeneousBag
+
+case object PeripherySPIKey extends Field[Seq[SPIParams]]
+
+trait HasPeripherySPI { this: BaseSubsystem =>
+  val spiParams = p(PeripherySPIKey)  
+  val spis = spiParams.zipWithIndex.map { case(params, i) =>
+    val name = Some(s"spi_$i")
+    val spi = LazyModule(new TLSPI(pbus.beatBytes, params)).suggestName(name)
+    pbus.toVariableWidthSlave(name) { spi.rnode }
+    ibus.fromSync := spi.intnode
     spi
   }
 }
 
-trait PeripherySPIBundle {
-  this: { val spiConfigs: Seq[SPIConfig] } =>
-  val spi_bc = spiConfigs.map(_.bc).reduce(_.union(_))
-  val spis = Vec(spiConfigs.size, new SPIPortIO(spi_bc.toSPIConfig))
+trait HasPeripherySPIBundle {
+  val spi: HeterogeneousBag[SPIPortIO]
+
 }
 
-trait PeripherySPIModule {
-  this: TopNetworkModule {
-    val spiConfigs: Seq[SPIConfig]
-    val outer: PeripherySPI
-    val io: PeripherySPIBundle
-  } =>
-  (io.spis zip outer.spi).foreach { case (io, device) =>
+trait HasPeripherySPIModuleImp extends LazyModuleImp with HasPeripherySPIBundle {
+  val outer: HasPeripherySPI
+  val spi = IO(HeterogeneousBag(outer.spiParams.map(new SPIPortIO(_))))
+
+  (spi zip outer.spis).foreach { case (io, device) =>
     io <> device.module.io.port
   }
 }
 
+case object PeripherySPIFlashKey extends Field[Seq[SPIFlashParams]]
 
-trait PeripherySPIFlash {
-  this: TopNetwork { val spiFlashConfig: SPIFlashConfig } =>
-  val qspi = LazyModule(new TLSPIFlash(spiFlashConfig))
-  qspi.rnode := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
-  qspi.fnode := TLFragmenter(1, cacheBlockBytes)(TLWidthWidget(peripheryBusConfig.beatBytes)(peripheryBus.node))
-  intBus.intnode := qspi.intnode
+trait HasPeripherySPIFlash { this: BaseSubsystem =>
+  val spiFlashParams = p(PeripherySPIFlashKey)  
+  val qspis = spiFlashParams.zipWithIndex.map { case(params, i) =>
+    val name = Some(s"qspi_$i")
+    val qspi = LazyModule(new TLSPIFlash(pbus.beatBytes, params))
+    pbus.toVariableWidthSlave(name) { qspi.rnode }
+    qspi.fnode := pbus.toFixedWidthSlave(name) {
+      TLFragmenter(1, pbus.blockBytes) :=
+        TLBuffer(BufferParams(params.fBufferDepth), BufferParams.none)
+    }
+    ibus.fromSync := qspi.intnode
+    qspi
+  }
 }
 
-trait PeripherySPIFlashBundle {
-  this: { val spiFlashConfig: SPIFlashConfig } =>
-  val qspi = new SPIPortIO(spiFlashConfig)
+trait HasPeripherySPIFlashBundle {
+  val qspi: HeterogeneousBag[SPIPortIO]
+
 }
 
-trait PeripherySPIFlashModule {
-  this: TopNetworkModule {
-    val spiConfigs: Seq[SPIConfig]
-    val outer: PeripherySPIFlash
-    val io: PeripherySPIFlashBundle
-  } =>
-  io.qspi <> outer.qspi.module.io.port
+trait HasPeripherySPIFlashModuleImp extends LazyModuleImp with HasPeripherySPIFlashBundle {
+  val outer: HasPeripherySPIFlash
+  val qspi = IO(HeterogeneousBag(outer.spiFlashParams.map(new SPIPortIO(_))))
+
+  (qspi zip outer.qspis) foreach { case (io, device) => 
+    io <> device.module.io.port
+  }
 }