Use HomogenousBag to handle lists of peripherals

[sifive-blocks.git] / src / main / scala / devices / spi / SPIPeriphery.scala

diff --git a/src/main/scala/devices/spi/SPIPeriphery.scala b/src/main/scala/devices/spi/SPIPeriphery.scala
index 40bcec692f9265f5b9fa590a09a060194244ff23..bdd74c66a041e8aaa80f90df21c3855768015361 100644 (file)
--- a/src/main/scala/devices/spi/SPIPeriphery.scala
+++ b/src/main/scala/devices/spi/SPIPeriphery.scala
@@ -5,11 +5,12 @@ import Chisel._
 import diplomacy.LazyModule
 import uncore.tilelink2._
 import rocketchip.{TopNetwork,TopNetworkModule}
+import util.HeterogeneousBag
 
 trait PeripherySPI {
   this: TopNetwork { val spiConfigs: Seq[SPIConfig] } =>
-  val spiDevices = (spiConfigs.zipWithIndex) map {case (c, i) =>
-    val spi = LazyModule(new TLSPI(c) { override lazy val valName = Some(s"spi$i") } )
+  val spi = (spiConfigs.zipWithIndex) map {case (c, i) =>
+    val spi = LazyModule(new TLSPI(c))
     spi.rnode := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
     intBus.intnode := spi.intnode
     spi
@@ -18,8 +19,7 @@ trait PeripherySPI {
 
 trait PeripherySPIBundle {
   this: { val spiConfigs: Seq[SPIConfig] } =>
-  val spi_bc = spiConfigs.map(_.bc).reduce(_.union(_))
-  val spis = Vec(spiConfigs.size, new SPIPortIO(spi_bc.toSPIConfig))
+  val spis = HeterogeneousBag(spiConfigs.map(new SPIPortIO(_)))
 }
 
 trait PeripherySPIModule {
@@ -28,7 +28,7 @@ trait PeripherySPIModule {
     val outer: PeripherySPI
     val io: PeripherySPIBundle
   } =>
-  (io.spis zip outer.spiDevices).foreach { case (io, device) =>
+  (io.spis zip outer.spi).foreach { case (io, device) =>
     io <> device.module.io.port
   }
 }