SPI: Make it easier to build arbitrary bundles

[sifive-blocks.git] / src / main / scala / devices / spi / SPIPins.scala

diff --git a/src/main/scala/devices/spi/SPIPins.scala b/src/main/scala/devices/spi/SPIPins.scala
index 346f8ee63d820e6fae8436858332b06ebe0b04a8..c46e90a84efe144f04488ac8d7a668e83d4e5eca 100644 (file)
--- a/src/main/scala/devices/spi/SPIPins.scala
+++ b/src/main/scala/devices/spi/SPIPins.scala
@@ -5,13 +5,23 @@ import Chisel._
 import chisel3.experimental.{withClockAndReset}
 import sifive.blocks.devices.pinctrl.{PinCtrl, Pin}
 
-class SPIPins[T <: Pin] (pingen: ()=> T, c: SPIParamsBase) extends SPIBundle(c) {
+class SPISignals[T <: Data] (pingen: ()=> T, c: SPIParamsBase) extends SPIBundle(c) {
 
-  val sck: T      = pingen()
-  val dq: Vec[T]  = Vec(4, pingen())
-  val cs: Vec[T]  = Vec(c.csWidth, pingen())
+  val sck = pingen()
+  val dq  = Vec(4, pingen())
+  val cs  = Vec(c.csWidth, pingen())
 
-  def fromSPIPort(spi: SPIPortIO, clock: Clock, reset: Bool,
+  override def cloneType: this.type =
+    this.getClass.getConstructors.head.newInstance(pingen, c).asInstanceOf[this.type]
+
+}
+
+class SPIPins[T <: Pin] (pingen: ()=> T, c: SPIParamsBase) extends SPISignals(pingen, c) {
+
+  override def cloneType: this.type =
+    this.getClass.getConstructors.head.newInstance(pingen, c).asInstanceOf[this.type]
+
+  def fromPort(spi: SPIPortIO, clock: Clock, reset: Bool,
     syncStages: Int = 0, driveStrength: Bool = Bool(false)) {
 
     withClockAndReset(clock, reset) {