package sifive.blocks.devices.spi
import Chisel._
-import config._
-import diplomacy._
-import regmapper._
-import uncore.tilelink2._
-
+import freechips.rocketchip.config.Parameters
+import freechips.rocketchip.diplomacy._
+import freechips.rocketchip.regmapper._
+import freechips.rocketchip.tilelink._
+import freechips.rocketchip.util.HeterogeneousBag
import sifive.blocks.util.{NonBlockingEnqueue, NonBlockingDequeue}
trait SPIParamsBase {
require(sampleDelay >= 0)
}
-class SPITopBundle(val i: util.HeterogeneousBag[Vec[Bool]], val r: util.HeterogeneousBag[TLBundle]) extends Bundle
+class SPITopBundle(val i: HeterogeneousBag[Vec[Bool]], val r: HeterogeneousBag[TLBundle]) extends Bundle
class SPITopModule[B <: SPITopBundle](c: SPIParamsBase, bundle: => B, outer: TLSPIBase)
extends LazyModuleImp(outer) {
abstract class TLSPIBase(w: Int, c: SPIParamsBase)(implicit p: Parameters) extends LazyModule {
require(isPow2(c.rSize))
- val device = new SimpleDevice("spi", Seq("sifive,spi0")) {
- override def describe(resources: ResourceBindings): Description = {
- val Description(name, mapping) = super.describe(resources)
- val rangesSeq = resources("ranges").map(_.value)
- val ranges = if (rangesSeq.isEmpty) Map() else Map("ranges" -> rangesSeq)
- Description(name, mapping ++ ranges)
- }
- }
-
+ val device = new SimpleDevice("spi", Seq("sifive,spi0"))
val rnode = TLRegisterNode(address = Seq(AddressSet(c.rAddress, c.rSize-1)), device = device, beatBytes = w)
val intnode = IntSourceNode(IntSourcePortSimple(resources = device.int))
}