spi: add dts ranges field for memory mapped spi (#19)

[sifive-blocks.git] / src / main / scala / devices / spi / TLSPI.scala

diff --git a/src/main/scala/devices/spi/TLSPI.scala b/src/main/scala/devices/spi/TLSPI.scala
index b20b5246c3e5a813ee51e67f16d0712a56c6bede..5833fad7a9669c85d2c8b1a6cdce9d3282f63d7c 100644 (file)
--- a/src/main/scala/devices/spi/TLSPI.scala
+++ b/src/main/scala/devices/spi/TLSPI.scala
@@ -109,8 +109,16 @@ class SPITopModule[B <: SPITopBundle](c: SPIParamsBase, bundle: => B, outer: TLS
 
 abstract class TLSPIBase(w: Int, c: SPIParamsBase)(implicit p: Parameters) extends LazyModule {
   require(isPow2(c.rSize))
-  val device = new SimpleDevice("spi", Seq("sifive,spi0"))
-  val rnode = TLRegisterNode(address = AddressSet(c.rAddress, c.rSize-1), device = device, beatBytes = w)
+  val device = new SimpleDevice("spi", Seq("sifive,spi0")) {
+    override def describe(resources: ResourceBindings): Description = {
+      val Description(name, mapping) = super.describe(resources)
+      val rangesSeq = resources("ranges").map(_.value)
+      val ranges = if (rangesSeq.isEmpty) Map() else Map("ranges" -> rangesSeq)
+      Description(name, mapping ++ ranges)
+    }
+  }
+
+  val rnode = TLRegisterNode(address = Seq(AddressSet(c.rAddress, c.rSize-1)), device = device, beatBytes = w)
   val intnode = IntSourceNode(IntSourcePortSimple(resources = device.int))
 }