package sifive.blocks.devices.spi
import Chisel._
-import config._
-import uncore.tilelink2._
-import diplomacy._
-import regmapper._
-import junctions._
-import rocketchip.PeripheryBusConfig
+import freechips.rocketchip.config.Parameters
+import freechips.rocketchip.diplomacy._
+import freechips.rocketchip.regmapper._
+import freechips.rocketchip.tilelink._
+import freechips.rocketchip.interrupts._
+import freechips.rocketchip.util.HeterogeneousBag
import sifive.blocks.util.{NonBlockingEnqueue, NonBlockingDequeue}
-trait SPIConfigBase {
+trait SPIParamsBase {
val rAddress: BigInt
val rSize: BigInt
val rxDepth: Int
}
-case class SPIConfig(
+case class SPIParams(
rAddress: BigInt,
rSize: BigInt = 0x1000,
rxDepth: Int = 8,
delayBits: Int = 8,
divisorBits: Int = 12,
sampleDelay: Int = 2)
- extends SPIConfigBase {
+ extends SPIParamsBase {
require(frameBits >= 4)
require(sampleDelay >= 0)
}
-class SPITopBundle(val i: Vec[Vec[Bool]], val r: Vec[TLBundle]) extends Bundle
-
-class SPITopModule[B <: SPITopBundle](c: SPIConfigBase, bundle: => B, outer: TLSPIBase)
+class SPITopModule(c: SPIParamsBase, outer: TLSPIBase)
extends LazyModuleImp(outer) {
- val io = new Bundle {
+ val io = IO(new Bundle {
val port = new SPIPortIO(c)
- val tl = bundle
- }
+ })
val ctrl = Reg(init = SPIControl.init(c))
val ie = Reg(init = new SPIInterrupts().fromBits(Bits(0)))
val ip = fifo.io.ip
- io.tl.i(0)(0) := (ip.txwm && ie.txwm) || (ip.rxwm && ie.rxwm)
+ val (io_int, _) = outer.intnode.out(0)
+ io_int(0) := (ip.txwm && ie.txwm) || (ip.rxwm && ie.rxwm)
protected val regmapBase = Seq(
SPICRs.sckdiv -> Seq(RegField(c.divisorBits, ctrl.sck.div)),
RegField.r(1, ip.rxwm)))
}
-abstract class TLSPIBase(c: SPIConfigBase)(implicit p: Parameters) extends LazyModule {
+abstract class TLSPIBase(w: Int, c: SPIParamsBase)(implicit p: Parameters) extends LazyModule {
require(isPow2(c.rSize))
- val rnode = TLRegisterNode(address = AddressSet(c.rAddress, c.rSize-1), beatBytes = p(PeripheryBusConfig).beatBytes)
- val intnode = IntSourceNode(1)
+ val device = new SimpleDevice("spi", Seq("sifive,spi0"))
+ val rnode = TLRegisterNode(address = Seq(AddressSet(c.rAddress, c.rSize-1)), device = device, beatBytes = w)
+ val intnode = IntSourceNode(IntSourcePortSimple(resources = device.int))
}
-class TLSPI(c: SPIConfig)(implicit p: Parameters) extends TLSPIBase(c)(p) {
- lazy val module = new SPITopModule(c, new SPITopBundle(intnode.bundleOut, rnode.bundleIn), this) {
+class TLSPI(w: Int, c: SPIParams)(implicit p: Parameters) extends TLSPIBase(w,c)(p) {
+ lazy val module = new SPITopModule(c, this) {
mac.io.link <> fifo.io.link
rnode.regmap(regmapBase:_*)
}