spi: Make memory mapped interface depth a parameter

[sifive-blocks.git] / src / main / scala / devices / spi / TLSPIFlash.scala

diff --git a/src/main/scala/devices/spi/TLSPIFlash.scala b/src/main/scala/devices/spi/TLSPIFlash.scala
index fc786f58ff8488ccde6d49217b7425f8b0a6c609..e433fec05e39f94701dd1bba76532faecad2c065 100644 (file)
--- a/src/main/scala/devices/spi/TLSPIFlash.scala
+++ b/src/main/scala/devices/spi/TLSPIFlash.scala
@@ -2,14 +2,16 @@
 package sifive.blocks.devices.spi
 
 import Chisel._
-import config._
-import diplomacy._
-import regmapper._
-import uncore.tilelink2._
+import freechips.rocketchip.config.Parameters
+import freechips.rocketchip.diplomacy._
+import freechips.rocketchip.regmapper._
+import freechips.rocketchip.tilelink._
+import freechips.rocketchip.util.HeterogeneousBag
 
 trait SPIFlashParamsBase extends SPIParamsBase {
   val fAddress: BigInt
   val fSize: BigInt
+  val fBufferDepth: Int
 
   val insnAddrBytes: Int
   val insnPadLenBits: Int
@@ -21,6 +23,7 @@ trait SPIFlashParamsBase extends SPIParamsBase {
 case class SPIFlashParams(
     rAddress: BigInt,
     fAddress: BigInt,
+    fBufferDepth: Int = 0,
     rSize: BigInt = 0x1000,
     fSize: BigInt = 0x20000000,
     rxDepth: Int = 8,
@@ -38,7 +41,7 @@ case class SPIFlashParams(
   require(sampleDelay >= 0)
 }
 
-class SPIFlashTopBundle(i: util.HeterogeneousBag[Vec[Bool]], r: util.HeterogeneousBag[TLBundle], val f: util.HeterogeneousBag[TLBundle]) extends SPITopBundle(i, r)
+class SPIFlashTopBundle(i: HeterogeneousBag[Vec[Bool]], r: HeterogeneousBag[TLBundle], val f: HeterogeneousBag[TLBundle]) extends SPITopBundle(i, r)
 
 class SPIFlashTopModule[B <: SPIFlashTopBundle]
     (c: SPIFlashParamsBase, bundle: => B, outer: TLSPIFlashBase)
@@ -65,7 +68,7 @@ class SPIFlashTopModule[B <: SPIFlashTopBundle]
   flash.io.addr.valid := f.a.valid
   f.a.ready := flash.io.addr.ready
 
-  f.d.bits := outer.fnode.edgesIn.head.AccessAck(a, UInt(0), flash.io.data.bits)
+  f.d.bits := outer.fnode.edgesIn.head.AccessAck(a, flash.io.data.bits)
   f.d.valid := flash.io.data.valid
   flash.io.data.ready := f.d.ready
 
@@ -95,7 +98,7 @@ abstract class TLSPIFlashBase(w: Int, c: SPIFlashParamsBase)(implicit p: Paramet
   require(isPow2(c.fSize))
   val fnode = TLManagerNode(1, TLManagerParameters(
     address     = Seq(AddressSet(c.fAddress, c.fSize-1)),
-    resources   = Seq(Resource(device, "ranges")),
+    resources   = device.reg("mem"),
     regionType  = RegionType.UNCACHED,
     executable  = true,
     supportsGet = TransferSizes(1, 1),