package sifive.blocks.devices.uart
import Chisel._
-import config._
-import regmapper._
-import uncore.tilelink2._
-import util._
+import freechips.rocketchip.config.Parameters
+import freechips.rocketchip.regmapper._
+import freechips.rocketchip.tilelink._
+import freechips.rocketchip.util._
import sifive.blocks.util.{NonBlockingEnqueue, NonBlockingDequeue}
address: BigInt,
dataBits: Int = 8,
stopBits: Int = 2,
+ divisorInit: Int = 0,
divisorBits: Int = 16,
oversample: Int = 4,
nSamples: Int = 3,
def c: UARTParams
def uartDataBits = c.dataBits
def uartStopBits = c.stopBits
+ def uartDivisorInit = c.divisorInit
def uartDivisorBits = c.divisorBits
def uartOversample = c.oversample
def uartNTxEntries = c.nTxEntries
def uartNRxEntries = c.nRxEntries
+ require(uartDivisorInit != 0) // should have been initialized during instantiation
require(uartDivisorBits > uartOversample)
require(uartOversampleFactor > uartNSamples)
}
val rxm = Module(new UARTRx(params))
val rxq = Module(new Queue(rxm.io.out.bits, uartNRxEntries))
- val divinit = 542 // (62.5MHz / 115200)
- val div = Reg(init = UInt(divinit, uartDivisorBits))
+ val div = Reg(init = UInt(uartDivisorInit, uartDivisorBits))
private val stopCountBits = log2Up(uartStopBits)
private val txCountBits = log2Floor(uartNTxEntries) + 1