val rxm = Module(new UARTRx(params))
val rxq = Module(new Queue(rxm.io.out.bits, uartNRxEntries))
- val divinit = 542 // (62.5MHz / 115200)
+ val divinit = p(diplomacy.DTSTimebase) * p(rocketchip.RTCPeriod) / 115200
val div = Reg(init = UInt(divinit, uartDivisorBits))
private val stopCountBits = log2Up(uartStopBits)
// Magic TL2 Incantation to create a TL2 UART
class TLUART(w: Int, c: UARTParams)(implicit p: Parameters)
- extends TLRegisterRouter(c.address, interrupts = 1, beatBytes = w)(
+ extends TLRegisterRouter(c.address, "serial", Seq("sifive,uart0"), interrupts = 1, beatBytes = w)(
new TLRegBundle(c, _) with HasUARTTopBundleContents)(
new TLRegModule(c, _, _) with HasUARTTopModuleContents)